US5029126A
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Cache memory
Assignee: Panasonic Holdings Corp
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Filing: 1989-08-03
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Granted: 1991-07-02
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Expires: 2009-08-03
Abstract
Abstract A set associative type cache memory incorporated in a microprocessor includes memory arrays arranged in a group for each line, and only a memory array selected by a line address selected at the time of operation is made operative, thus reducing power consumption.
Inventors
- 👤 Seiji Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:18
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F2212/00; G06F2212/10; G06F2212/1028; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
238 words
A cache memory of a set associative type incorporated in a semiconductor integrated circuit, wherein the number of sets, which indicates a number of data pieces which can be read out during a single access operation to said cache memory, is represented by m (where m is an integer and is greater than 1), the number of blocks, which indicates a number of accessible tag addresses contained in one set, is represented by l (where l is a power of 2), the number of lines, which indicates a number of accessible addresses contained in one block is represented by n (where n is a power of 2 and is greater than l), and the number of data bits per line, block and set is represented by k (where k is an integer), said cache memory comprising: n memory array areas, each of said memory array areas containing l x m x k bits; and data buses connected respectively to said memory array areas to receive and transfer data, each of said data buses being of k bits, wherein said memory array areas are grouped into a plurality of pairs, and respective sets of each pair of said memory array areas are arranged symmetrically with respect to a respective one of said data buses so that the respective sets of each pair of said memory array areas are connected in common to said respective one of said data buses.
Claim 2
Dependent Claim
238 words
A cache memory of a set associative type incorporated in a semiconductor integrated circuit, wherein the number of sets, which indicates a number of data pieces which can be read out during a single access operation to said cache memory, is represented by m (where m is an integer and is greater than 1), the number of blocks, which indicates a number of accessible tag addresses contained in one set, is represented by l (where l is a power of 2), the number of lines, which indicates a number of accessible addresses contained in one block is represented by n (where n is a power of 2 and is greater than l), and the number of data bits per line, block and set is represented by k (where k is an integer), said cache memory comprising: n memory array areas, each of said memory array areas containing l x m x k bits; and data buses connected respectively to said memory array areas to receive and transfer data, each of said data buses being of k bits, wherein said memory array areas are grouped into a plurality of pairs, and respective sets of each pair of said memory array areas are arranged symmetrically with respect to a respective one of said data buses so that the respective sets of each pair of said memory array areas are connected in common to said respective one of said data buses.
Claim 3
Dependent Claim
278 words
A cache memory of a set associative type incorporated in a semiconductor integrated circuit, wherein the number of sets, which indicates a number of data pieces which can be read out during a single access operation to said cache memory, is represented by m (where m is an integer and is greater than 1), the number of blocks, which indicates a number of accessible tag addresses contained in one set, is represented by l (where l is a power of 2), the number of lines, which indicates a number of accessible addresses contained in one block is represented by n (where n is power of 2 and is greater than l), and the number of data bits per line, block and set is represented by k (where k is an integer), said cache memory comprising: n memory array areas, each of said memory array areas containing l x m x k bits; and data buses connected respectively to said memory array areas to receive and transfer data, each of said data buses being of k bits, wherein said memory array areas are grouped into a plurality of pairs, and respective sets of each pair of said memory array areas are arranged symmetrically with respect to a respective one of said data buses so that the respective sets of each pair of said memory array areas are connected in common to said respective one of said data buses, and only one of said n memory array areas, which is selected by a line address, is caused to be operative when said cache memory is in operation, while the remaining (n-1) memory array areas are maintained in an inoperative condition.
Claim 4
Dependent Claim
278 words
A cache memory of a set associative type incorporated in a semiconductor integrated circuit, wherein the number of sets, which indicates a number of data pieces which can be read out during a single access operation to said cache memory, is represented by m (where m is an integer and is greater than 1), the number of blocks, which indicates a number of accessible tag addresses contained in one set, is represented by l (where l is a power of 2), the number of lines, which indicates a number of accessible addresses contained in one block is represented by n (where n is power of 2 and is greater than l), and the number of data bits per line, block and set is represented by k (where k is an integer), said cache memory comprising: n memory array areas, each of said memory array areas containing l x m x k bits; and data buses connected respectively to said memory array areas to receive and transfer data, each of said data buses being of k bits, wherein said memory array areas are grouped into a plurality of pairs, and respective sets of each pair of said memory array areas are arranged symmetrically with respect to a respective one of said data buses so that the respective sets of each pair of said memory array areas are connected in common to said respective one of said data buses, and only one of said n memory array areas, which is selected by a line address, is caused to be operative when said cache memory is in operation, while the remaining (n-1) memory array areas are maintained in an inoperative condition.
Claim 5
Dependent Claim
16 words
A cache memory according to claim 1, wherein m is an odd number greater than 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |