US5727180A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory including master and local word lines coupled to memory cells storing access information
Assignee: International Business Machines Corp
•
Filing: 1995-06-07
•
Granted: 1998-03-10
•
Expires: 2015-06-07
Abstract
Abstract An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/least recently used (LRU) cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. The master word lines and local word lines having approximately the same cycle time. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The architecture circuitry efficiently updates the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.
Inventors
- 👤 Andrew Davis
- 👤 David Wills Milton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:18
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/12; G06F12/121; G06F12/123; G06F2212/00; G06F2212/10; G06F2212/1028; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
A cache formed on an integrated circuit chip for storing data fetched from a main storage means, the cache comprising: a plurality of index lines, each of said index lines having a first plurality of memory cells in a first storage area for storing main memory data and a second plurality of memory cells in a second storage for storing access information corresponding to said main memory data, said first and second storage areas having approximately same cycle time and said second storage area being accessed before said first storage area; a first controller receiving said access information for a selected one of index lines for detecting whether any of said main memory data stored in said first storage area is to be accessed, and an array controller for selectively deactivating, in response to said access information, at least a portion of said first storage area of said selected one of said plurality of index lines that were previously electrically activated for enabling access thereto before and access cycle thereto has been completed; wherein said first and second plurality of memory cells for storing both data and access information for the data are coupled to the same index line.
Claim 2
Dependent Claim
199 words
A cache formed on an integrated circuit chip for storing data fetched from a main storage means, the cache comprising: a plurality of index lines, each of said index lines having a first plurality of memory cells in a first storage area for storing main memory data and a second plurality of memory cells in a second storage for storing access information corresponding to said main memory data, said first and second storage areas having approximately same cycle time and said second storage area being accessed before said first storage area; a first controller receiving said access information for a selected one of index lines for detecting whether any of said main memory data stored in said first storage area is to be accessed, and an array controller for selectively deactivating, in response to said access information, at least a portion of said first storage area of said selected one of said plurality of index lines that were previously electrically activated for enabling access thereto before and access cycle thereto has been completed; wherein said first and second plurality of memory cells for storing both data and access information for the data are coupled to the same index line.
Claim 3
Dependent Claim
24 words
The cache of claim 1, wherein said second storage area stores at least one tag address on each of said plurality of index lines.
Claim 4
Dependent Claim
43 words
The cache of claim 2, wherein said second storage area stores bits, on each of said plurality of index lines, indicating the validity of said main memory data stored on respective ones of said plurality of index lines in said first storage area.
Claim 5
Dependent Claim
37 words
The cache of claim 3, wherein each of said plurality of index lines stores a plurality of main memory data words, each of said plurality of main memory data words comprising a plurality of addressable data words.
Claim 6
Dependent Claim
52 words
The cache of claim 4, wherein said second storage area stores a plurality of bits on each of said plurality of index lines providing a relative indication of how recently each of said plurality of main memory data words stored on a respective one of said plurality of index lines was accessed.
Claim 7
Dependent Claim
237 words
A cache formed on an integrated circuit chip for storing data fetched from a main storage means, the cache comprising: a plurality of index lines, each of said index lines having a first plurality of memory cells in a first storage area for storing main memory data and a second plurality of memory cells in a second storage for storing access information corresponding to said main memory data, said first and second storage areas having approximately a same cycle time and said second storage area being accessed before said first storage area; decoding means for electrically activating at least a subset of said first storage area for enabling access thereto in response to receiving access information sent to the cache; a first controller receiving said access information corresponding to said main memory data for a selected one of said plurality of index lines for detecting whether any of said main memory data stored in said first storage area is to be accessed; and an array controller for selectively deactivating, in response to said access information, at least a portion of said first storage area of said selected one of said plurality of index lines that were previously electrically activated for enabling access thereto before and access cycle thereto has been completed; wherein said first and second plurality of memory cells for storing both data and access information for the data are coupled to the same index line.
Claim 8
Dependent Claim
237 words
A cache formed on an integrated circuit chip for storing data fetched from a main storage means, the cache comprising: a plurality of index lines, each of said index lines having a first plurality of memory cells in a first storage area for storing main memory data and a second plurality of memory cells in a second storage for storing access information corresponding to said main memory data, said first and second storage areas having approximately a same cycle time and said second storage area being accessed before said first storage area; decoding means for electrically activating at least a subset of said first storage area for enabling access thereto in response to receiving access information sent to the cache; a first controller receiving said access information corresponding to said main memory data for a selected one of said plurality of index lines for detecting whether any of said main memory data stored in said first storage area is to be accessed; and an array controller for selectively deactivating, in response to said access information, at least a portion of said first storage area of said selected one of said plurality of index lines that were previously electrically activated for enabling access thereto before and access cycle thereto has been completed; wherein said first and second plurality of memory cells for storing both data and access information for the data are coupled to the same index line.
Claim 9
Dependent Claim
220 words
A cache formed on an integrated circuit chip for storing data fetched from a main storage means, the cache comprising: a plurality of index lines, each of said index lines having a first plurality of memory cells in a first storage area for storing main memory data and a second plurality of memory cells in a second storage for storing access information corresponding to said main memory data, said first and second storage areas having approximately same cycle time and said second storage area being accessed before said first storage area; a first controller receiving said access information corresponding to said main memory data for a selected one of said plurality of index lines for detecting whether any of said main memory data stored in said first storage area is to be accessed; and an array controller for selectively deactivating, in response to said access information, all but one of a plurality of cache lines of said first storage area of said selected one of said plurality of index lines, that were previously electrically activated for enabling access thereto at a beginning of an access cycle thereto, before said access cycle has been completed; wherein said first and second plurality of memory cells for storing both data and access information for the data are coupled to the same index line.
Claim 10
Dependent Claim
220 words
A cache formed on an integrated circuit chip for storing data fetched from a main storage means, the cache comprising: a plurality of index lines, each of said index lines having a first plurality of memory cells in a first storage area for storing main memory data and a second plurality of memory cells in a second storage for storing access information corresponding to said main memory data, said first and second storage areas having approximately same cycle time and said second storage area being accessed before said first storage area; a first controller receiving said access information corresponding to said main memory data for a selected one of said plurality of index lines for detecting whether any of said main memory data stored in said first storage area is to be accessed; and an array controller for selectively deactivating, in response to said access information, all but one of a plurality of cache lines of said first storage area of said selected one of said plurality of index lines, that were previously electrically activated for enabling access thereto at a beginning of an access cycle thereto, before said access cycle has been completed; wherein said first and second plurality of memory cells for storing both data and access information for the data are coupled to the same index line.
References Cited (Backward Citations)
US4714990A
Cited
US4719568A
Cited
US4596000A
Cited
US4907150A
Cited
US5237671A
Cited
US4914582A
Cited
US4811209A
Cited
US5014240A
Cited
US5019971A
Cited
US4910656A
Cited
US5018061A
Cited
US5113510A
Cited
US5241639A
Cited
EP0352806A2
Cited
US5029126A
Cited
US5202969A
Cited
US5060136A
Cited
US5067078A
Cited
US5155824A
Cited
US5091851A
Cited
US5233702A
Cited
US5206941A
Cited
US5241664A
Cited
US5175833A
Cited
US5210842A
Cited
US5367660A
Cited
US5345411A
Cited
US5367653A
Cited
US5524233A
Cited
US5502683A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |