Cache memory with multiple valid bits for each data indication the validity within different contents

Claim 1

A cache memory for a computer that accesses memory in a first context during the execution of a first program and in a second context during the execution of a second program, the cache memory comprising: a collection of addressable memory locations, each location of which is apportioned into a data memory portion paired with a tag memory portion; means for addressing the addressable memory locations; a first valid bit within each tag memory portion and representing the validity within the first context of the content of the data memory portion paired therewith; a second valid bit within each tag memory portion and representing the validity within the second context of the content of the data memory portion paired therewith; means for simultaneously clearing each first valid bit in response to a change in the first context; means for simultaneously clearing each second valid bit in response to a change in the second context; and means coupled to the first and second valid bits and responsive to a selection signal, for producing an output indicative of the state of the selected valid bit for the addressed tag memory portion.