Four-way associative cache with dlat and separately addressable arrays used for updating certain bits without reading them out first

Claim 1

A computer system comprising: a four-way associative cache having groups of memory locations, each of said groups comprising four associative classes, said cache including means for coupling to a CPU and permitting said CPU to individually access each of said associative classes; means for determining which associative class is currently being accessed by said CPU; a storage array for storing indications of relative order of access by said CPU to the associative classes within each group, said array including a separately addressable entry for each group, said storage array also storing parity bits for each of said entries; and storage array control means, coupled to said storage array and the determining means, for directly updating, without first reading, the entry in said storage array corresponding to the group containing the associative class that is currently being accessed by said CPU with an indication of relatively recent access to said associative class compared to other associative classes within said group, and writing the respective parity bits for the entry; and wherein there are exactly four associative classes within each group, each of said entries of said storage array utilizes exactly three bits to indicate said relative order of access, and there is a one-to-one correspondence between each of said parity bits and each bit of the corresponding entry in said storage array; and said storage array control means sets one of the three bits of the entry corresponding to the currently accessed group to indicate that two of the associative classes within the group have not been accessed by the current access, and sets another one of the three bits to indicate that one of the other two of the associative classes within the gorup has not been accessed by the current access.