US5210842A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor having instruction varied set associative cache boundary accessing
Assignee: NXP USA Inc
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Filing: 1991-02-04
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Granted: 1993-05-11
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Expires: 2011-02-04
Abstract
Abstract A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor operation codes are partially decoded within an intermediate stage of an instruction pipe of the data processor to provide information on pending instructions. The information provided determines if a pending instruction will require either a full or a partial output line of information from the set associative cache. When the provided information from the instruction pipe indicates that an instruction will require a full output line of information to complete execution, the set associative cache provides the full output line of information. Otherwise, the set associative cache provides only a partial output line of information.
Inventors
- 👤 Lal C. Sood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:53
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0886; G06F12/0875; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3818; G06F9/382; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
260 words
A data processor having instruction varied set associative cache boundary accessing, comprising: instruction processing and decoding means for receiving a plurality of successive instructions and decoding the successive instructions, the instruction decoding means providing a set associative cache boundary control signal for a subsequent set associative cache access; set associative cache control means having an input coupled to the instruction processing and decoding means for receiving the set associative cache boundary control signal and providing an encoded enable signal; a set associative cache coupled to set associative cache control means for receiving the encoded enable signal and having a predetermined number of lines of information of predetermined bit length, said set associative cache using the encoded enable signal to dynamically select one of a plurality of predetermined lengths of a line of information to be accessed in the set associative cache and provided by the set associative cache, the set associative cache normally providing only one-half line of information in response to the encoded enable signal in order to conserve power in the data processor and providing a full line of information only in response to the data processor requiring the complete line of information; a holding register having an input coupled to the set associative cache and having an output, the holding register storing information from the set associative cache; and a multiplecor having an input coupled to the output of the holding register, and having an output coupled to the instruction processing and decoding means for providing a selected portion of information provided by the set associative cache.
Claim 2
Dependent Claim
260 words
A data processor having instruction varied set associative cache boundary accessing, comprising: instruction processing and decoding means for receiving a plurality of successive instructions and decoding the successive instructions, the instruction decoding means providing a set associative cache boundary control signal for a subsequent set associative cache access; set associative cache control means having an input coupled to the instruction processing and decoding means for receiving the set associative cache boundary control signal and providing an encoded enable signal; a set associative cache coupled to set associative cache control means for receiving the encoded enable signal and having a predetermined number of lines of information of predetermined bit length, said set associative cache using the encoded enable signal to dynamically select one of a plurality of predetermined lengths of a line of information to be accessed in the set associative cache and provided by the set associative cache, the set associative cache normally providing only one-half line of information in response to the encoded enable signal in order to conserve power in the data processor and providing a full line of information only in response to the data processor requiring the complete line of information; a holding register having an input coupled to the set associative cache and having an output, the holding register storing information from the set associative cache; and a multiplecor having an input coupled to the output of the holding register, and having an output coupled to the instruction processing and decoding means for providing a selected portion of information provided by the set associative cache.
Claim 3
Dependent Claim
46 words
The data processor of claim 1 further comprising: a communications bus coupled between the instruction processing and decoding means and the set associative cache and having a predetermined bit width of more bits than one or more of the lengths in the plurality of predetermined lengths.
Claim 4
Dependent Claim
17 words
The data processor of claim 1 wherein the set associative cache is a four-way set associative cache.
Claim 5
Dependent Claim
21 words
The data processor of claim 1 wherein the set associative cache is one of an instruction cache or a data cache.
Claim 6
Dependent Claim
221 words
In a data processing system having a set associative cache, a method for varying a boundary within a line of information accessed, comprising the steps of: receiving a plurality of successive instructions and decoding the successive instructions with a central processing unit of the data processing system; for each decoding of the successive instructions, providing a set associative cache boundary control signal for a subsequent set associative cache access; providing an encoded enable signal in response to each set associative cache boundary control signal; and accessing a set associative cache having a predetermined number of lines of information of predetermined bit length and using the encoded enable signal to dynamically select a length of a line of information to be accessed in the set associative cache and provided by the set associative cache, the selected length normally being one-half of the line of information to conserve power in the data processing system and being a complete line of information only in response to the data processing system requiring the complete line of information; storing the selected length of the line of information in a holding register circuit; and multiplexing a portion of the stored selected length of the line of information by transferring a predetermined portion of the stored selected length of the line of information to the central processing unit.
Claim 7
Dependent Claim
221 words
In a data processing system having a set associative cache, a method for varying a boundary within a line of information accessed, comprising the steps of: receiving a plurality of successive instructions and decoding the successive instructions with a central processing unit of the data processing system; for each decoding of the successive instructions, providing a set associative cache boundary control signal for a subsequent set associative cache access; providing an encoded enable signal in response to each set associative cache boundary control signal; and accessing a set associative cache having a predetermined number of lines of information of predetermined bit length and using the encoded enable signal to dynamically select a length of a line of information to be accessed in the set associative cache and provided by the set associative cache, the selected length normally being one-half of the line of information to conserve power in the data processing system and being a complete line of information only in response to the data processing system requiring the complete line of information; storing the selected length of the line of information in a holding register circuit; and multiplexing a portion of the stored selected length of the line of information by transferring a predetermined portion of the stored selected length of the line of information to the central processing unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |