High-speed partitioned set associative cache memory

Claim 2

A high-speed partitioned set associative cache memory, comprising: high-speed cache memory data array means associated with a CPU, said cache memory data array means having a plurality of individual partial data array boards which together comprise said memory data array, a full tag array mounted on each of the individual data array boards and coupled to an individual partial data array, a plurality of memory address registers, at least one mounted on each partial data array board and associated with each individual partial data array and each individual tag array on each of the data array boards, said memory address registers being adapted to receive an address from said CPU and for simultaneously accessing said partial data arrays and said tag arrays on all of said data array boards, logic circuit and control means mounted on a separate board from said plurality of individual partial data array boards for monitoring output error signals from said data arrays and from said tag arrays resulting from accessing memory addresses, and means for subsequently identifying the exact data or tag array where an error has occurred.

Claim 3

A high-speed partitioned set associative cache memory as set forth in claim 1 wherein each individual partial data array board of said cache memory data array means comprises a plurality of modules, each said module comprising a plurality of memory chips, and a plurality of said address registers mounted on each partial data array board in close proximity to said modules of said memory chips.

Claim 4

A high-speed partitioned set associative cache memory as set forth in claim 2 wherein each full tag array on each partial data array board comprises the plurality of modules, and each of said tag array modules comprising a plurality of memory chips in close proximity to one of said address registers.

Claim 5

A high-speed partitioned set associative cache memory as set forth in claim 1 wherein said plurality of individual partial data array boards each contain a portion of a full word and each tag array on each of said individual partial data array boards each contains full tag addresses, said logic and control means being mounted on a separate board for monitoring error output signals from said individual data arrays, and said logic circuit and control means further comprising data parity error means for checking parity error output signals from each selected block of said individual partial data array boards.

Claim 6

A high-speed partitioned set associative cache memory as set forth in claim 4 wherein said logic circuit and control means further comprises error decode means coupled to the output of said tag array and to the output of said data parity error means for decoding tag array comparison errors.

Claim 7

A high-speed partitioned set associative cache memory as set forth in claim 5 wherein said logic circuit and control means further comprises error status logic means coupled to the output of said error decoding means.

Claim 8

A high-speed partitioned set associative cache memory as set forth in claim 6 wherein said logic circuit and control means further comprises degrade means coupled to the output of said error status logic means for degrading a portion of said cache memory where an error has been identified.

Claim 9

A high-speed partitioned set associative cache memory as set forth in claim 6 wherein said logic circuit and control means further comprises interrupt sequence control means coupled to the output of said error status logic and to said CPU for interrupting the normal sequence of operation of said CPU.

Claim 10

A high-speed partitioned set associative cache memory as set forth in claim 4 wherein said logic and control means further comprise latch means coupled to the output of said logic and control means for maintaining a detected error condition.

Claim 11

A high-speed partitioned set associative cache memory as set forth in claim 9 which further includes truth table logic means coupled to said latch means for determining the module within the tag array where an error has occurred.

Claim 12

A high-speed partitioned set assciative cache memory as set forth in claim 1 wherein said logic circuit and control means further comprises a multi phase clock adapted to access said partial data array addresses in a phase 1 operation and to access said full tag array and to enable the proper data paths from said partial data arrays during a phase 3 operation to provide output data during a clock cycle time.

Claim 13

A high-speed partitioned set associative cache memory as set forth in claim 11 wherein said logic circuit and control means further comprises means for comparing the outputs of all of said plurality of individual partial data array boards and full tag array with each other and for determining which board of said plurality of individual partial data array boards contains an error.

Claim 14

A high-speed partitioned set associative cache memory as set forth in claim 12 which further includes tag match comparison means for determining which board of said plurality of individual partial data array boards contains a tag error.

Claim 15

A high-speed partitioned set associative cache memory as set forth in claim 13 which further includes means for determining the type of error detected in said tag array or said data array.

Claim 16

A high-speed partitioned set associative cache memory as set forth in claim 14 which further includes error status logic means for correcting the error detected in said partial data array or said full tag arrays.

Claim 17

A high-speed partitioned set associative cache memory, comprising: high-speed cache memory data array means associated with a CPU, said cache memory data array means having a plurality of individual partial data array boards which together comprise said memory data array, a full tag array mounted on each of the individual data array boards and coupled to an individual partial data array, a plurality of memory address registers, at least one mounted on each partial data array board and associated with each individual partial data array and each individual tag array on each of the data array boards, said memory address registers being adapted to receive an address from said CPU and for simultaneously accessing said partial data arrays and said tag arrays on all of said data array boards, logic circuit and control means mounted on a separate board from said plurality of individual partial data array boards for monitoring output error signals from said data arrays and from said tag arrays resulting from accessing memory addresses, said logic circuit and control means having a multi phase clock adapted to access said partial data array addresses in one clock phase and to access said full tag array and to enable the proper data paths from said partial data arrays in a subsequent clock phase to provide output data during a clock cycle time, and means for subsequently identifying the exact data or tag array where an error has occurred.

Claim 18

A high-speed partitioned set associative cache memory, comprising: high-speed cache memory data array means associated with a CPU, said cache memory data array means having a plurality of individual partial data array boards which together comprise said memory data array, a full tag array mounted on each of the individual data array boards and coupled to an individual partial data array, a plurality of memory address registers, at least one mounted on each partial data array board and associated with each individual partial data array and each individual tag array on each of the data array boards, said memory address registers being adapted to receive an address from said CPU and for simultaneously accessing said partial data arrays and said tag arrays on all of said data array boards, logic circuit and control means mounted on a separate board from said plurality of individual partial data array boards for monitoring output error signals from said data arrays and from said tag arrays resulting from accessing memory addresses, said logic circuit and control means having a multi phase clock adapted to access said partial data array addresses in one clock phase and to access said full tag array and to enable the proper data paths from said partial data arrays in a subsequent clock phase to provide output data during a clock cycle time, and means for subsequently identifying the exact data or tag array where an error has occurred.

Claim 19

A high-speed partitioned set associative cache memory as set forth in claim 16 wherein said one clock phase and said subsequent clock phase comprise phases of the same clock cycle.