Configurable set associative cache with decoded data element enable lines

Claim 2

A set associative cache for operating on an input main memory address, the input main memory address including a tag field and index field, comprising: A. a tag array providing, in response to the index field, a plurality of tag elements in parallel, the plurality of tag elements being equal to a predetermined maximum set size into which the cache can be configured; B. a plurality of tag comparators, each tag comparator arranged to receive a corresponding one of the tag elements and the tag field, and each tag comparator asserting a corresponding tag hit signal when its received tag element matches the tag field; C. a data array providing, in response to the index field, a plurality of data elements, the plurality of data elements being equal to the predetermined maximum set size; D. a data element select logic circuit providing, in response to the tag field and the plurality of tag hit signals, a plurality of decoded data element enable signals, the plurality of decoded data element enable signals being equal to the predetermined maximum set size; and E. multiplexing means, arranged to receive the plurality of data elements and the plurality of decoded data element enable signals, for enabling access to a selected one of the data elements.

Claim 3

An apparatus as in claim 1 wherein the multiplexing means comprises a plurality of bi-directional transceivers, each transceiver coupled to receive a corresponding one of the data elements at one input port and coupled to the other transceivers at another input port.

Claim 4

An apparatus as in claim 1 wherein the data element select logic is also responsive to a signal indicating the current number of sets into which the cache is arranged, additionally comprising: F. means for generating the signal indicating the current number of sets into which the cache is arranged.

Claim 5

A set associative cache for operating on an input main memory address, the input main memory address including a tag field and index field, comprising: A. tag array means, responsive to the index field, for providing a plurality of tag elements in parallel, the number of tag elements equal to a predetermined maximum set size into which the cache can be configured; B. data array means, responsive to the index field, for providing a plurality of data elements in parallel, the number of data elements equal to the predetermined maximum set size; C. means for allowing concurrent access to the tag array contents and the data array contents; D. a plurality of tag comparator means, each responsive to a corresponding one of the tag elements from the tag array and also responsive to the tag field from the input main memory address, for asserting a tag hit signal when the corresponding tag element from the tag array matches the tag field from the input main memory address; and E. means for deferring the enablement of access to a desired one of the data elements until the corresponding tag hit signal is asserted by the tag comparator means corresponding to the desired data element.

Claim 6

A set associative cache for operating on an input main memory address, the input main memory address including a tag field and index field, comprising: A. tag array means, responsive to the index field, for providing a plurality of tag elements in parallel, the number of tag elements equal to a predetermined maximum set size into which the cache can be configured; B. data array means, responsive to the index field, for providing a plurality of data elements in parallel, the number of data elements equal to the predetermined maximum set size; C. means for allowing concurrent access to the tag array contents and the data array contents; D. a plurality of tag comparator means, each responsive to a corresponding one of the tag elements from the tag array and also responsive to the tag field from the input main memory address, for asserting a tag hit signal when the corresponding tag element from the tag array matches the tag field from the input main memory address; and E. means for deferring the enablement of access to a desired one of the data elements until the corresponding tag hit signal is asserted by the tag comparator means corresponding to the desired data element.

Claim 7

A data processing system comprising: a central processing unit providing memory address signals at an output, the memory address signals including a tag field and index field; a set associative cache for receiving the memory address signals and for selectively asserting or not-asserting a cache hit signal in response thereto; and main memory means, for receiving the memory address signals and the cache hit signal, and for enabling access to the set associative cache by the central processing unit when the cache hit signal is not asserted, wherein the set associative cache additionally comprises: A. a tag array providing, in response to the index field, a plurality of tag elements in parallel, the plurality of tag elements equal to a predetermined maximum set size into which the cache can be configured; B. a plurality of tag comparators, each tag comparator arranged to receive a corresponding one of the tag elements and the tag field, and each tag comparator asserting a corresponding tag hit signal when its received tag element matches the tag field; C. a data array providing, in response to the index field, a plurality of data elements, the plurality of data elements also equal to the predetermined maximum set size; D. a data element select logic circuit providing, in response to the tag field and the plurality of tag hit signals, a plurality of decoded data element enable signals, the plurality of decoded enable signals equal to the predetermined maximum set size, the data element select logic circuit also asserting the cache hit signal when any of the tag hit signals is asserted; and E. multiplexing means, arranged to receive the plurality of data elements and the plurality of decoded data element enable signals, for enabling access to a selected one of the data elements by the central processor.

Claim 8

A data processing system comprising: a central processing unit providing memory address signals at an output, the memory address signals including a tag field and index field; a set associative cache for receiving the memory address signals and for selectively asserting or not-asserting a cache hit signal in response thereto; and main memory means, for receiving the memory address signals and the cache hit signal, and for enabling access to the set associative cache by the central processing unit when the cache hit signal is not asserted, wherein the set associative cache additionally comprises: A. a tag array providing, in response to the index field, a plurality of tag elements in parallel, the plurality of tag elements equal to a predetermined maximum set size into which the cache can be configured; B. a plurality of tag comparators, each tag comparator arranged to receive a corresponding one of the tag elements and the tag field, and each tag comparator asserting a corresponding tag hit signal when its received tag element matches the tag field; C. a data array providing, in response to the index field, a plurality of data elements, the plurality of data elements also equal to the predetermined maximum set size; D. a data element select logic circuit providing, in response to the tag field and the plurality of tag hit signals, a plurality of decoded data element enable signals, the plurality of decoded enable signals equal to the predetermined maximum set size, the data element select logic circuit also asserting the cache hit signal when any of the tag hit signals is asserted; and E. multiplexing means, arranged to receive the plurality of data elements and the plurality of decoded data element enable signals, for enabling access to a selected one of the data elements by the central processor.

Claim 9

A cache controller for enabling access to a cache memory element in response to an input memory address, the input memory address including a tag field and an index field, the cache controller comprising: A. tag array means, responsive to the index field, for providing a plurality of tag elements in parallel, the number of tag elements being equal to a predetermined maximum set size; B. a plurality of tag comparators, each tag comparator arranged to receive a corresponding one of the tag elements and the tag field, and each tag comparator asserting a corresponding tag hit signal when its received tag element matches the tag field; and C. a data element select logic circuit providing, in response to the tag field and the plurality of tag hit signals, a plurality of decoded data element enable signals, the number of decoded data element enable signals being equal to the predetermined maximum set size.

Claim 10

A cache controller for enabling access to a cache memory element in response to an input memory address, the input memory address including a tag field and an index field, the cache controller comprising: A. tag array means, responsive to the index field, for providing a plurality of tag elements in parallel, the number of tag elements being equal to a predetermined maximum set size; B. a plurality of tag comparators, each tag comparator arranged to receive a corresponding one of the tag elements and the tag field, and each tag comparator asserting a corresponding tag hit signal when its received tag element matches the tag field; and C. a data element select logic circuit providing, in response to the tag field and the plurality of tag hit signals, a plurality of decoded data element enable signals, the number of decoded data element enable signals being equal to the predetermined maximum set size.

Claim 11

An apparatus as in claim 6 wherein the data element select logic circuit is also responsive to a signal indicating the current number of sets into which the cache is arranged, additionally comprising: D. means for generating the signal indicating the current number of sets into which the cache is arranged.