High availability cache organization

Claim 2

A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, said status field including a force bit having a set state that indicates a physically defective, nonoperational condition and a reset state that indicates a normal condition of a cache memory cell associated with said force bit; read means for reading data from said cache memory including means for addressing a prescribed set of said cache memory cells, means for comparing said tag field for each cache memory cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to the reset state of said force bit and to said hit signal for enabling one of the cache memory cells in said prescribed set to provide its data field to said central processing unit; write means for storing data from said main memory in said prescribed set of cache memory cells; means for determining that a cache memory cell is in a physically defective, nonoperational condition and for setting said force bit for the physically defective cache memory cell to the set state; and means responsive to the set state of said force bit for the physically defective cache memory cell for suppressing data read therefrom and for preventing storage of data in the physically defective memory cell.

Claim 3

A cache memory as defined in claim 1 wherein said read means further includes means for checking parity of said data field and of said tag field and providing a parity error signal when a parity error is found, and wherein said output enable means is responsive to said parity error signal to inhibit the cache memory cell for which the parity error was found from providing its data field to said central processing unit.

Claim 4

A cache memory as defined in claim 2 wherein said status field further includes an update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set and wherein said write means further includes replacement selection means responsive to the update bit for each of said cache memory cells in the prescribed set of said cache memory cells for selecting which cache memory cell of the prescribed set of said cache memory cells is to have its data replaced and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced.

Claim 5

A cache memory as defined in claim 3 wherein said replacement selection means is further responsive to said force bit to avoid storing data in any cache memory cell which has its force bit set.

Claim 6

A cache memory as defined in claim 3 wherein said replacement selection means employs a first-in first-out algorithm.

Claim 7

A cache memory as defined in claim 2 wherein said status field further includes an update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set and wherein said write means further includes replacement selection means responsive to the update bit for each of said cache memory cells in the prescribed set of said cache memory cells for selecting which cache memory cell of the prescribed set of said cache memory cells is to have its data replaced and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced, and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is accessed by said central processing unit.

Claim 8

A cache memory as defined in claim 2 wherein said status field further includes only a single update bit for each memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set and wherein said write means further includes replacement selection means responsive to the update bit for each of said cache memory cells for selecting which cache memory cell of the prescribed set of said cache memory cells is to have its data replaced and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced, and when the replacement selection means selects the cache memory cell as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 9

A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, said status field including update information consisting of only a single update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory including means for addressing a prescribed set of said cache memory cells, means for comparing said tag field for each cache memory cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to said hit signal for enabling one of the cache memory cells in said prescribed set to provide its data field to said central processing unit; and write means for storing data from said main memory in said prescribed set of cache memory cells including replacement selection means responsive to the update bit for each of said cache memory cells in the prescribed set of said cache memory cells for selecting which cache memory cell of the prescribed set of said cache memory cells is to have its data replaced, and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 10

A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, said status field including update information consisting of only a single update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory including means for addressing a prescribed set of said cache memory cells, means for comparing said tag field for each cache memory cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to said hit signal for enabling one of the cache memory cells in said prescribed set to provide its data field to said central processing unit; and write means for storing data from said main memory in said prescribed set of cache memory cells including replacement selection means responsive to the update bit for each of said cache memory cells in the prescribed set of said cache memory cells for selecting which cache memory cell of the prescribed set of said cache memory cells is to have its data replaced, and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 11

A cache memory as defined in claim 8 wherein said status field further includes a force bit which indicates a physically defective, nonoperational cache memory cell when it is set and wherein said replacement selection means is further responsive to said force bit to avoid storing data in any cache memory cell which has its force bit set.

Claim 12

A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including a force bit which indicates a physically defective condition of a cache memory cell associated with said force bit; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; means for determining that a cache memory cell is in a physically defective, nonoperational condition and for setting said force bit for the cache memory cell that is in a physically defective, nonoperational condition; and means responsive to said force bit indicating a physically defective, nonoperational condition for suppressing data read from said cache memory cell associated with said force bit indicating a physically defective, nonoperational condition and for preventing storing data in said cache memory cell associated with said force bit indicating a physically defective, nonoperational condition.

Claim 13

A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including a force bit which indicates a physically defective condition of a cache memory cell associated with said force bit; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; means for determining that a cache memory cell is in a physically defective, nonoperational condition and for setting said force bit for the cache memory cell that is in a physically defective, nonoperational condition; and means responsive to said force bit indicating a physically defective, nonoperational condition for suppressing data read from said cache memory cell associated with said force bit indicating a physically defective, nonoperational condition and for preventing storing data in said cache memory cell associated with said force bit indicating a physically defective, nonoperational condition.

Claim 14

A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including update information consisting of only a single update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; and replacement selection means responsive to the update bits in a set of cache memory cells for selecting a cache memory cell of said set for replacement and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 15

A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including update information consisting of only a single update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; and replacement selection means responsive to the update bits in a set of cache memory cells for selecting a cache memory cell of said set for replacement and means for changing said update bit when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 16

A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including an update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; and replacement selection means responsive to the update bit for each of said cache memory cells in a set of cache memory cells for selecting a cache memory cell of said set for replacement and means for changing said update bit only when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is accessed by said central processing unit.

Claim 17

A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including an update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; and replacement selection means responsive to the update bit for each of said cache memory cells in a set of cache memory cells for selecting a cache memory cell of said set for replacement and means for changing said update bit only when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is accessed by said central processing unit.

Claim 18

A cache memory as defined in claim 12 wherein said replacement selection means employs a first-in-first-out algorithm.

Claim 19

A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including update information consisting of only a single update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; and replacement selection means responsive to the update bit for each of said cache memory cells in a set of cache memory cells for selecting a cache memory cell of said set for replacement and means for changing said update bit only when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 20

A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache memory cells including a data field, a tag field and a status field that are stored in commonly addressed storage locations and are commonly accessed for reading and writing, and each of the sets of cache memory cells including a cache memory cell from each of said memory elements, each status field including update information consisting of only a single update bit for each cache memory cell, the update bits for a set of cache memory cells collectively indicating an update status of the set; read means for reading data from said cache memory cells; write means for storing data in said cache memory cells; and replacement selection means responsive to the update bit for each of said cache memory cells in a set of cache memory cells for selecting a cache memory cell of said set for replacement and means for changing said update bit only when the data in said cache memory cell associated with said update bit is replaced and when the replacement selection means selects the cache memory cell associated with said update bit as next to have its data replaced and the data field associated with said update bit is stored with data from said central processing unit.

Claim 21

A cache memory as defined in claim 14 wherein said replacement selection means employs a first-in-first-out algorithm.