US5018061A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor with on-chip cache memory with lower power consumption
Assignee: Toshiba Corp
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Filing: 1988-06-27
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Granted: 1991-05-21
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Expires: 2008-06-27
Abstract
Abstract A microprocessor with on-cache memory and an address translation buffer in which it further comprises first and second flip-flop circuits for indicating in hit or miss in the tag field of the cache memory and for storing which of the X and Y sections of the tag field a target data exists. Access to the tag field is carried out prior to access to the data field of the cache memory, thereby preventing access to the data field when a miss occurs in the tag field, and thus decreasing power consumption.
Inventors
- 👤 Hidechica Kishigami
- 👤 Tohru Sasaki
- 👤 Kiyotaka Sasai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F2212/00; G06F2212/10; G06F2212/1028; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
324 words
A microprocessor for performing instruction execution by using pipelined processing, comprising: a logical address register, which stores a logical address of a memory read or write operand; a physical address register, which stores a physical address of a memory read or write operand; a translation lookaside buffer (TLB), coupled to said logical address register and physical address register, to receive an upper value of the logical address, convert the upper value into a corresponding upper value of the physical address, and send it to said physical address register; an on-chip cache memory comprising a tag memory having at least two (X and Y) sections and data memory also having at least two (X and Y) sections, said tag memory being coupled to said logical address register and containing a plurality of upper values of physical addresses for data in said data memory, said data memory being coupled to said physical address register and receiving a lower value of the physical address in said physical address register wherein access by the logical address to said tag memory is carried out prior to a corresponding access of the data memory by the physical address; comparator means for comparing the upper value of physical address from said TLB and the upper value of physical addresses from sections (X and Y) of said tag memory and for outputting a result of comparison; first storage means, coupled to said comparator means and said data memory, for storing the result of comparison indicating in which of the sections (X or Y) of said data memory a target data exists, and controlling said data memory so that only one of said sections (X and Y) is accessed; and second storage means, coupled to said comparator means and said data memory, for storing the result of comparison which is a cache hit or a cache miss, and controlling said data memory to be accessed only when the result shows a cache hit.
Claim 2
Dependent Claim
324 words
A microprocessor for performing instruction execution by using pipelined processing, comprising: a logical address register, which stores a logical address of a memory read or write operand; a physical address register, which stores a physical address of a memory read or write operand; a translation lookaside buffer (TLB), coupled to said logical address register and physical address register, to receive an upper value of the logical address, convert the upper value into a corresponding upper value of the physical address, and send it to said physical address register; an on-chip cache memory comprising a tag memory having at least two (X and Y) sections and data memory also having at least two (X and Y) sections, said tag memory being coupled to said logical address register and containing a plurality of upper values of physical addresses for data in said data memory, said data memory being coupled to said physical address register and receiving a lower value of the physical address in said physical address register wherein access by the logical address to said tag memory is carried out prior to a corresponding access of the data memory by the physical address; comparator means for comparing the upper value of physical address from said TLB and the upper value of physical addresses from sections (X and Y) of said tag memory and for outputting a result of comparison; first storage means, coupled to said comparator means and said data memory, for storing the result of comparison indicating in which of the sections (X or Y) of said data memory a target data exists, and controlling said data memory so that only one of said sections (X and Y) is accessed; and second storage means, coupled to said comparator means and said data memory, for storing the result of comparison which is a cache hit or a cache miss, and controlling said data memory to be accessed only when the result shows a cache hit.
Claim 3
Dependent Claim
69 words
The microprocessor as claimed in claim 1, wherein a total number of bits to be processed is 32 bits and the upper 20 bits in said logical address register are converted by the TLB into the upper 20 bits in said physical address register, and the lower 12 bits in said logical address register are directly set to the lower 12 bits in said physical address register without conversion.
Claim 4
Dependent Claim
49 words
The microprocessor as claimed in claim 1, wherein eight bits from the bit positions 20 to 27 in said logical address register are applied to said tag memory and eight bits from the bit positions 20 to 27 in said physical address register are applied to said data memory.
Claim 5
Dependent Claim
325 words
A cache and translation lookaside buffer system using pipelined processing, comprising: a logical address register, which stores a logical address of a memory read or write operand; a physical address register, which stores a physical address of a memory read or write operand; a translation lookaside buffer (TLB), coupled to said logical address register and said physical address register, to receive an upper value of the logical address, convert the upper value into a corresponding upper value of the physical address, and send it to said physical address register; a cache memory comprising a tag memory having at least two (X and Y) sections and a data memory having at least two (X and Y) sections, said tag memory being coupled to said logical address register and containing a plurality of upper values of physical addresses for data in said data memory, said data memory being coupled to said physical address register and receiving a lower value of the physical address in said physical address register wherein access by the logical address to said tag memory is carried out prior to a corresponding access of the data memory by the physical address; comparator means for comparing the upper value of physical address from said TLB and the upper value of physical addresses from sections (X and Y) of said tag memory and for outputting a result of comparison; first storage means, coupled to said comparator means and said data memory, for storing the result of comparison indicating in which of the sections (X or Y) of said data memory a target data exists, and controlling said data memory so that only one of said sections (X and Y) is accessed; and a second storage means, coupled to said comparator means and said data memory, for storing the result of comparison which is a cache hit or a cache miss, and controlling said data memory to be accessed only when the result shows a cache hit.
Claim 6
Dependent Claim
325 words
A cache and translation lookaside buffer system using pipelined processing, comprising: a logical address register, which stores a logical address of a memory read or write operand; a physical address register, which stores a physical address of a memory read or write operand; a translation lookaside buffer (TLB), coupled to said logical address register and said physical address register, to receive an upper value of the logical address, convert the upper value into a corresponding upper value of the physical address, and send it to said physical address register; a cache memory comprising a tag memory having at least two (X and Y) sections and a data memory having at least two (X and Y) sections, said tag memory being coupled to said logical address register and containing a plurality of upper values of physical addresses for data in said data memory, said data memory being coupled to said physical address register and receiving a lower value of the physical address in said physical address register wherein access by the logical address to said tag memory is carried out prior to a corresponding access of the data memory by the physical address; comparator means for comparing the upper value of physical address from said TLB and the upper value of physical addresses from sections (X and Y) of said tag memory and for outputting a result of comparison; first storage means, coupled to said comparator means and said data memory, for storing the result of comparison indicating in which of the sections (X or Y) of said data memory a target data exists, and controlling said data memory so that only one of said sections (X and Y) is accessed; and a second storage means, coupled to said comparator means and said data memory, for storing the result of comparison which is a cache hit or a cache miss, and controlling said data memory to be accessed only when the result shows a cache hit.
Claim 7
Dependent Claim
75 words
The cache and translation lookaside buffer (TLB) system as claimed in claim 4, wherein a total number of bits to be processed is 32 bits and the upper 20 bits in said logical address register are converted by the TLB into the upper 20 bits in said physical address register, and the lower 12 bits in said logical address register are directly set to the lower 12 bits in said physical address register without conversion.
References Cited (Backward Citations)
US3761881A
Cited
US3764996A
Cited
US4577293A
Cited
US4823259A
Cited
US4794524A
Cited
US4725945A
Cited
US4691277A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |