US4823259A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed buffer store arrangement for quick wide transfer of data
Assignee: International Business Machines Corp
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Filing: 1988-06-23
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Granted: 1989-04-18
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Expires: 2008-06-23
Abstract
Abstract A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.
Inventors
- 👤 Frederick J. Aichelmann, Jr.
- 👤 Rex H. Blumberg
- 👤 David Meltzer
- 👤 James H. Pomerene
- 👤 Thomas R. Puzak
- 👤 Rudolph N. Rechtschaffen
- 👤 Frank J. Sparacio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:01
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
410 words
A cache module for permitting the efficient transfer of m byte wide data entities between a fast, level L1 cache and a slower level L2 cache in a single access of said L1 and L2 cache, where m bytes is the width of a single cache line and is greater than 16 bytes, wherein: said L1 cache includes an array of n memory circuits, such that n times the number p bits accessed per memory circuit equals m, and further having m byte wide input means and m byte wide output means for respectively receiving and transmitting said m byte wide data entity between said L1 and L2 caches; said L2 cache including an array of x memory circuits, such that x times the number y bits accessed per memory circuit equals m, and further having m byte wide input means and m byte wide output means for respectively receiving and transmitting said m byte wide data entity between said L1 and L2 caches; intercache bus for coupling said L1 and said L2 caches comprising first m byte wide coupling means for coupling said L1 cache output means to said L2 cache input means and second m byte wide coupling means for coupling said L2 cache output means to said L1 cache input means; a common main storage data bus coupled to said main storage, said main storage data bus having a width that is a fraction w/m of said inter-cache bus first and second m byte wide coupling means width, said input means of said L1 and L2 caches being coupled to said common main storage data bus; at least one output data bus having a width of m bytes coupled to said output means of said L1 and L2 caches; first converter means for sequentially furnishing fractions of a w/m wide data block to said processor and/or said main storage data bus having only said fractional width w/m, said first converter means being coupled to said output means of said L1 and L2 caches via said at least one output data bus; register array means having a capacity of at least m data bytes coupled to said output data bus, for storing at least one data block of m bytes from said first converter means; and second converter means coupled to said register array means, for sequentially furnishing fractions of any m-byte data block stored in said register array means to said processor and/or main storage data bus.
Claim 2
Dependent Claim
410 words
A cache module for permitting the efficient transfer of m byte wide data entities between a fast, level L1 cache and a slower level L2 cache in a single access of said L1 and L2 cache, where m bytes is the width of a single cache line and is greater than 16 bytes, wherein: said L1 cache includes an array of n memory circuits, such that n times the number p bits accessed per memory circuit equals m, and further having m byte wide input means and m byte wide output means for respectively receiving and transmitting said m byte wide data entity between said L1 and L2 caches; said L2 cache including an array of x memory circuits, such that x times the number y bits accessed per memory circuit equals m, and further having m byte wide input means and m byte wide output means for respectively receiving and transmitting said m byte wide data entity between said L1 and L2 caches; intercache bus for coupling said L1 and said L2 caches comprising first m byte wide coupling means for coupling said L1 cache output means to said L2 cache input means and second m byte wide coupling means for coupling said L2 cache output means to said L1 cache input means; a common main storage data bus coupled to said main storage, said main storage data bus having a width that is a fraction w/m of said inter-cache bus first and second m byte wide coupling means width, said input means of said L1 and L2 caches being coupled to said common main storage data bus; at least one output data bus having a width of m bytes coupled to said output means of said L1 and L2 caches; first converter means for sequentially furnishing fractions of a w/m wide data block to said processor and/or said main storage data bus having only said fractional width w/m, said first converter means being coupled to said output means of said L1 and L2 caches via said at least one output data bus; register array means having a capacity of at least m data bytes coupled to said output data bus, for storing at least one data block of m bytes from said first converter means; and second converter means coupled to said register array means, for sequentially furnishing fractions of any m-byte data block stored in said register array means to said processor and/or main storage data bus.
Claim 3
Dependent Claim
35 words
The cache module according to claim 1 wherein said input means and output means comprise, respectively, input latches and output latches, respectively, for holding data to be written into or read from said memory circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |