Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations

Claim 2

A processor for use in a computer system having an external cache that includes a plurality of lines storing information, said processor comprising: bus means coupled to the external cache for transferring the data and the plurality of instructions; and cache controlling means coupled to the bus means for controlling the external cache in response to interagent communications received from a memory, wherein the interagent communication comprises a plurality of control bits, wherein the cache controlling means performs cache control operations according to the setting of each of the plurality of control bits, such that the external cache is controlled from within the processor.

Claim 3

The processor as defined in claim 1 wherein the cache controlling means flushes a plurality of cache lines in the external cache in one operation in response to one of the interagent communications.

Claim 4

The processor as defined in claim 2 wherein the plurality of lines is specified in said one interagent communication.

Claim 5

The processor as defined in claim 1 wherein the cache controlling means invalidates a plurality of cache lines in the external cache in one operation in response to one of the interagent communications.

Claim 6

The processor as defined in claim 4 wherein the plurality of lines is specified in said one interagent communication.

Claim 7

The processor as defined in claim 1 wherein the cache controlling means modifies coherency state information associated with a line in the external cache in response to one of the interagent communications.

Claim 8

The processor as defined in claim 1 wherein the cache controlling means performs at least one operation on a plurality of lines of the cache based on an address range specified in each of the interagent communication.

Claim 9

The processor as defined in claim 1 wherein the cache control logic flushes a plurality of cache lines in the external cache in one operation in response to an interagent communication.

Claim 10

The computer system as defined in claim 1 wherein the memory storing the interagent communication comprises a dedicated set of registers in the processor.

Claim 11

The computer system as defined in claim 1 wherein the processor further comprises an event unit which indicates that the interagent communication exists and further comprises a means for branching to a microcode routine to handle the interagent communications.

Claim 12

The computer system as defined in claim 10 further comprising means for detecting existence of one of the interagent communications by detecting a specific address in an instruction executed by the processor.

Claim 13

The processor defined in claim 1 further comprising: an instruction fetching means coupled to the bus means for fetching the plurality of instructions; instruction decoding means coupled to the instruction fetching means for decoding the plurality of instructions; executing means coupled to the instruction decoding means for executing the plurality of instructions.

Claim 14

A processor for use in a computer system having an external cache memory and at least one other memory external to the processor, the processor comprising: an execution data path that processes information; a unit that receives a first interagent communication passed through said at least one other memory, said interagent communication specifying at least one cache control operation; a microcode engine for executing a set of microcode instructions that includes a routine to control the external cache according to said at least one cache control operation, such that at least one line of the external cache is flushed when said at least one cache control operation comprises a flush operation, at least one line of the external cache is invalidated when said at least one cache control operation comprises an invalidate operation, and coherency state of at least one line of the external cache is modified when said at least one cache control operation comprises a modify coherency operation.

Claim 15

A processor for use in a computer system having an external cache memory and at least one other memory external to the processor, the processor comprising: an execution data path that processes information; a unit that receives a first interagent communication passed through said at least one other memory, said interagent communication specifying at least one cache control operation; a microcode engine for executing a set of microcode instructions that includes a routine to control the external cache according to said at least one cache control operation, such that at least one line of the external cache is flushed when said at least one cache control operation comprises a flush operation, at least one line of the external cache is invalidated when said at least one cache control operation comprises an invalidate operation, and coherency state of at least one line of the external cache is modified when said at least one cache control operation comprises a modify coherency operation.

Claim 16

The processor as defined in claim 13 wherein further comprising a cache controller that operates in conjunction with the microcode engine to perform said at least one cache control operation.

Claim 17

The processor as defined in claim 13 further comprising a pin that indicates that the first interagent communication is present in said at least one other memory.

Claim 18

The processor as defined in claim 13 further comprising: means for sending a second interagent communication to one said other memory; and means for asserting an interagent communication pin on another device.

Claim 19

A processor for use in a computer system having an external cache, wherein the external cache includes a plurality of lines, said processor comprising: a control unit coupled to the external cache to transfer information; an executing unit coupled to the control unit that executes a plurality of instructions; and wherein the control unit includes cache control logic that controls the external cache in response to an interagent communication received from a memory, wherein the interagent communication includes a plurality of control bits, wherein the cache control logic performs cache control operations according to the setting of each of the plurality of control bits, such that the external cache is controlled from within the processor.

Claim 20

A processor for use in a computer system having an external cache, wherein the external cache includes a plurality of lines, said processor comprising: a control unit coupled to the external cache to transfer information; an executing unit coupled to the control unit that executes a plurality of instructions; and wherein the control unit includes cache control logic that controls the external cache in response to an interagent communication received from a memory, wherein the interagent communication includes a plurality of control bits, wherein the cache control logic performs cache control operations according to the setting of each of the plurality of control bits, such that the external cache is controlled from within the processor.

Claim 21

The processor as defined in claim 17 wherein source of the interagent communication is external to the processor.

Claim 22

The processor as defined in claim 17 wherein the cache controlling means invalidates a plurality of cache lines in the external cache in one operation in response to one of the interagent communications.

Claim 23

The processor as defined in claim 17 wherein the interagent communication further includes means for specifying an address range, such that the cache control logic performs cache control operations on the address range in the external cache according to the setting of each of the plurality of control bits.

Claim 24

The processor as defined in claim 20 wherein the means for specifying an address range comprises a starting address field for storing the starting address of the address range and an ending address field for storing the ending address of the address range.

Claim 25

The processor as defined in claim 17 wherein the cache control logic flushes at least one cache line in the external cache when at least one of the control bits is set.

Claim 26

The processor as defined in claim 17 wherein the cache control logic invalidates at least one cache line in the external cache when at least one of the control bits is set.

Claim 27

The processor as defined in claim 17 wherein the cache control logic modifies coherency state of at least one cache line in the external cache when at least one of the control bits is set.

Claim 28

A computer system comprising: bus means for communicating information; a memory means coupled to the bus means for storing information; a first processing means coupled to the bus means for executing the plurality of instructions; a cache memory means coupled to the first processing means for storing information requested by the first processing means, wherein the cache memory means includes a plurality of cache lines and is external to the first processing means; wherein the first processing means includes cache controlling means for controlling the cache memory means in response to an interagent communication passed through memory, such that at least one of the lines in the cache memory means is flushed, invalidated and/or its coherency state modified by the first processing means.

Claim 29

A computer system comprising: bus means for communicating information; a memory means coupled to the bus means for storing information; a first processing means coupled to the bus means for executing the plurality of instructions; a cache memory means coupled to the first processing means for storing information requested by the first processing means, wherein the cache memory means includes a plurality of cache lines and is external to the first processing means; wherein the first processing means includes cache controlling means for controlling the cache memory means in response to an interagent communication passed through memory, such that at least one of the lines in the cache memory means is flushed, invalidated and/or its coherency state modified by the first processing means.

Claim 30

The computer system as defined in claim 25 further comprising a second processing means for processing information, wherein the second processing means stores the interagent communication in the memory means and signals the first processing means that the interagent communication exists.

Claim 31

The computer system as defined in claim 25 wherein the means for indicating includes means for receiving a communication, wherein the communication depicts said at least one operation to be performed to the first processing means.

Claim 32

The computer system as defined in claim 27 wherein the source of the communication is internal to the first processing means.

Claim 33

The computer system as defined in claim 27 wherein the source of the communication is external to the first processing means.

Claim 34

The computer system as defined in claim 29 further comprising means for reading the interagent communication from said memory means.

Claim 35

The computer system as defined in claim 29 wherein the source of the communication is from a second processing means, wherein the second processing means causes assertion of a pin on the first processing means coupled to the bus means for executing at least one of the plurality of instructions.

Claim 36

A computer system comprising: a bus for communicating information; at least one memory coupled to the bus for storing information; a first processor coupled to the bus for executing a plurality of instructions; a cache memory coupled to the first processor for storing information requested by the first processor, wherein the cache memory includes a plurality of cache lines and is external to the first processing means; wherein the first processor includes circuit logic for receiving a interagent communication that indicates at least one cache control operation and cache control logic for controlling the cache memory in response to the interagent communication, and wherein the interagent communication comprises a plurality of bits for specifying at least one cache control operation and an address range, such that at least one of the lines in the cache memory is flushed, invalidated and/or its coherency state modified by the first processor according to the plurality of bits and the address range in the interagent communication.

Claim 37

A computer system comprising: a bus for communicating information; at least one memory coupled to the bus for storing information; a first processor coupled to the bus for executing a plurality of instructions; a cache memory coupled to the first processor for storing information requested by the first processor, wherein the cache memory includes a plurality of cache lines and is external to the first processing means; wherein the first processor includes circuit logic for receiving a interagent communication that indicates at least one cache control operation and cache control logic for controlling the cache memory in response to the interagent communication, and wherein the interagent communication comprises a plurality of bits for specifying at least one cache control operation and an address range, such that at least one of the lines in the cache memory is flushed, invalidated and/or its coherency state modified by the first processor according to the plurality of bits and the address range in the interagent communication.

Claim 40

The method as defined in claim 33 wherein the interagent communication specifies a flush operation, such that the second processor flushes at least one line of the external cache in response to reading and performing the cache control operation.

Claim 41

The method as defined in claim 33 wherein the interagent communication specifies to modify coherency state of the external cache, such that the second processor modifies the coherency state of at least one line of the external cache in response to reading and performing the cache control operation.

Claim 44

A computer system comprising: a bus that communicates information; a memory coupled to the bus that stores information; a first processor coupled to the bus that executes the plurality of instructions; an external cache coupled to the first processor that stores information requested by the first processor, wherein the cache includes a plurality of cache lines and is external to the first processor; wherein the first processor includes a cache control logic that controls the cache in response to an interagent communication received from a memory, wherein the interagent communication includes a plurality of control bits, wherein the cache control logic performs cache control operations according to the setting of each of the plurality of control bits, such that at least one of the lines in the cache memory is flushed, invalidated and/or its coherency state modified by the first processor.

Claim 45

A computer system comprising: a bus that communicates information; a memory coupled to the bus that stores information; a first processor coupled to the bus that executes the plurality of instructions; an external cache coupled to the first processor that stores information requested by the first processor, wherein the cache includes a plurality of cache lines and is external to the first processor; wherein the first processor includes a cache control logic that controls the cache in response to an interagent communication received from a memory, wherein the interagent communication includes a plurality of control bits, wherein the cache control logic performs cache control operations according to the setting of each of the plurality of control bits, such that at least one of the lines in the cache memory is flushed, invalidated and/or its coherency state modified by the first processor.

Claim 46

The computer system as defined in claim 37 wherein the cache control logic flushes a plurality of cache lines in the external cache in one operation in response to the interagent communication.

Claim 47

The computer system as defined in claim 37 wherein the control logic invalidates a plurality of cache lines in the external cache in one operation in response to the interagent communication.

Claim 48

The computer system as defined in claim 39 wherein the source of the interagent communication is internal to the first processor.

Claim 49

The computer system as defined in claim 39 wherein the source of the interagent communication is external to the first processor.

Claim 50

The computer system as defined in claim 41 further comprising circuit logic that reads the interagent communication from an external memory.

Claim 51

The computer system as defined in claim 41 wherein the source of interagent communication is from a second processor coupled to the bus.