US5345576A
Expired / Lapsed
US
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Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss
Abstract A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals. The microprocessor responds to the Bmiss signal by issuing the access onto the second bus in the event of a cache miss.
A data processing system comprising: a microprocessor fabricated on an integrated circuit chip; a main memory bus; a local bus connected to said microprocessor; a backside cache external to said integrated circuit chip, said backside cache including a directory RAM having cache address tag bits stored therein; a backside bus connected to said microprocessor and to said backside cache, said backside bus including backside bus cache address tag signals and backside bus cache directory state bits for determining a state encoding of a set in said directory RAM; a bus agent connected to said local bus and to said main memory bus; said backside bus further including a Bmis# signal; said directory RAM including means for comparing said cache address tag signals on said backside bus with said cache address tag bits stored in said directory RAM and for asserting said Bmis# signal upon a condition that said cache address tag bits stored in said directory RAM do not match said backside bus cache address tag signals; and, means in said microprocessor responsive to said Bmis# signal for issuing an address to said bus agent over said local bus.
Claim 2
Dependent Claim
189 words
A data processing system comprising: a microprocessor fabricated on an integrated circuit chip; a main memory bus; a local bus connected to said microprocessor; a backside cache external to said integrated circuit chip, said backside cache including a directory RAM having cache address tag bits stored therein; a backside bus connected to said microprocessor and to said backside cache, said backside bus including backside bus cache address tag signals and backside bus cache directory state bits for determining a state encoding of a set in said directory RAM; a bus agent connected to said local bus and to said main memory bus; said backside bus further including a Bmis# signal; said directory RAM including means for comparing said cache address tag signals on said backside bus with said cache address tag bits stored in said directory RAM and for asserting said Bmis# signal upon a condition that said cache address tag bits stored in said directory RAM do not match said backside bus cache address tag signals; and, means in said microprocessor responsive to said Bmis# signal for issuing an address to said bus agent over said local bus.
Claim 3
Dependent Claim
48 words
The combination in accordance with claim 1 wherein said backside cache is divided into instruction, data, private memory and I/O space and said bus agent includes signals to indicate which one of said instruction, data, private memory and I/O space of said backside cache an access maps into.
Claim 4
Dependent Claim
44 words
The combination in accordance with claim 1 further comprising: an internal cache directory RAM; said backside bus further including a Bcancel# signal; and, means in said processor for asserting said Bcancel# signal upon a condition that said access hit said internal cache directory RAM.