Selectively operable cache memory

Claim 1

A data processing apparatus comprising: (A) a cache memory having a plurality of data memory sections, each storing one or more data words, each said data memory section being operable to output a stored data word in response to an enable signal; a plurality of tag memory sections, each corresponding to a respective data memory section, said tag memory sections storing address information indicative of a memory address of each data word stored in said corresponding data memory section; and means for comparing a memory address of a required data word with said address information stored in said tag memory sections, said comparing means generating match signals indicating whether said required data word is stored in one of said data memory sections and, if so, identifying one of said data memory sections in which said required data word is stored; said cache memory being selectively operable in at least a first mode and a second mode, in which: (i) in said first mode, only that one of said data memory sections in which said required data word is stored is enabled for operation in response to said match signals; and (ii) in said second mode, two or more of said data memory sections are enabled for operation substantially concurrently with operation of said comparing means, said match signals being used to select the output of one of said data memory sections; (B) a prefetch unit for prefetching and buffering data processing instructions from said cache memory; and (C) means responsive to said instructions stored in said prefetch unit for controlling said cache memory to operate in either said first mode or said second mode of operation.