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EP0067657A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Computer system

Assignee: Fujitsu Ltd
•
Filing: 1982-06-09
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Granted: —
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Expires: 2002-06-09
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Abstract

Abstract In a computer system comprising a plurality of channels (10-0 to 10-31 at least one main storage unit (1-0 to 1-3), and a memory control unit (2) having a channel buffer (3) therebetween, the channel buffer comprises a tag portion (11) divided into a plurality of sets (SETO to SET 31) of blocks (11-0,11-1) of tag lines for storing control information (CTRL) and address information (ADDR) including a block address (ADDR 1 to 25) of a block of the main storage unit (1-0 to 1-3) and a data portion (12) having a plurality of data lines each corresponding to one of the tag lines. Each set of the tag portion is defined by one of the channels. The system is also includes a first access means (14, 26) for accessing the tag portion so as to select one tag line of each block of the tag portion; a second access means (19, 26) for accessing the data portion so as to select one data line thereof; a third access means (17, 26) for accessing the main storage unit; and, a comparator means (16-0, 16-1), connected to the tag portion, for comparing a block address stored in each tag line selected by the first access means with an access address of the channels to the main storage unit, so as to generate a matching signal (MCHO, MCH1) when both addresses are matched; whereby access to the data portion is carried out by the second access means when a matching signal is generated, while access to the main storage unit is carried out by the third access means when no matching signal is generated.

Inventors

  • 👤 Chiba Takashi
  • 👤 Koga Satoru

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 04:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F13/122

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 325 words
A computer system comprising: a plurality of channels (10-0 to 10-31); at least one central processing unit (6-0,6-1); at least one main storage unit (1-0 to 1-3); a memory control unit (2) connected to the channels, to the central processing unit, and to the main storage unit, for controlling data transmission between the channels, central processing unit and main storage unit; and, a channel buffer (3), included in the memory control unit, for controlling the memory storage unit and the channels; characterised in that the channel buffer comprises: a tag portion (11), divided into a plurality of sets (SETO to SET31) of blocks (11- 0 , 11-1) of tag lines for storing control information (CTRL) and address information (ADDR) including a block address (ADDR 1 to 25) of a block of the main storage unit, each set of the tag portion being defined by one of the channels, and a data portion (12) divided into a plurality of data lines each corresponding to one of the tag lines; and, in that the system also includes: a first access means (14, 26) for accessing the tag portion so as to select one tag line of each block of the tag portion; a second access means (19, 26) for accessing the data portion so as to select one data line thereof; a third access means (17, 26) for accessing the main storage unit; and, a comparator means (16-0, 16-1), connected to the tag portion, for comparing a block address stored in each tag line selected by the first access means with an access address of the channels to the main storage unit, so as to generate a matching signal (MCHO, MCH1) when both addresses are matched; whereby access to the data portion is carried out by the second access means when a matching signal is generated, while access to the main storage unit is carried out by the third access means when no matching signal is generated.
Claim 2
Dependent Claim 325 words
A computer system comprising: a plurality of channels (10-0 to 10-31); at least one central processing unit (6-0,6-1); at least one main storage unit (1-0 to 1-3); a memory control unit (2) connected to the channels, to the central processing unit, and to the main storage unit, for controlling data transmission between the channels, central processing unit and main storage unit; and, a channel buffer (3), included in the memory control unit, for controlling the memory storage unit and the channels; characterised in that the channel buffer comprises: a tag portion (11), divided into a plurality of sets (SETO to SET31) of blocks (11- 0 , 11-1) of tag lines for storing control information (CTRL) and address information (ADDR) including a block address (ADDR 1 to 25) of a block of the main storage unit, each set of the tag portion being defined by one of the channels, and a data portion (12) divided into a plurality of data lines each corresponding to one of the tag lines; and, in that the system also includes: a first access means (14, 26) for accessing the tag portion so as to select one tag line of each block of the tag portion; a second access means (19, 26) for accessing the data portion so as to select one data line thereof; a third access means (17, 26) for accessing the main storage unit; and, a comparator means (16-0, 16-1), connected to the tag portion, for comparing a block address stored in each tag line selected by the first access means with an access address of the channels to the main storage unit, so as to generate a matching signal (MCHO, MCH1) when both addresses are matched; whereby access to the data portion is carried out by the second access means when a matching signal is generated, while access to the main storage unit is carried out by the third access means when no matching signal is generated.
Claim 3
Dependent Claim 37 words
A computer according to claim 1, further comprising a fourth access means (41 to 45) for directly accessing the main storage unit when one of the channels requests a partial store access to the main storage unit.
Claim 4
Dependent Claim 43 words
A computer system according to claim 1 or 2, further comprising a fifth access means (51to63) for directly accessing the main storage unit when one of the channels requests an access for special data (CAW, CCW, DAT, CSW) to the main storage unit.
Claim 5
Dependent Claim 56 words
A computer system according to claim 1, 2 or 3, further comprising a prefetch means (24) for fetching the main storage unit when data is stored at a point over an intermediate point of each data line of the data portion so that fetch data is stored in the next data line of the data portion.

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