Cache memory addressable by both physical and virtual addresses

Claim 2

A cache memory addressable by both virtual and physical addresses, comprising: bus means for receiving an address for desired data. said address being virtual or physical and having an LSB portion comprised of a predetermined number of least significant bits and an MSB portion comprised of the remaining or most significant bits. the LSB portion of both the virtual and physical address being common for all addressed data; cache memory means for storing data, said stored data having a virtual and physical address associated therewith and addressable by the LSB portion of said received address for output from said cache memory means when the LSB portion of said received address corresponds to the LSB portion of the associated address of said stored data; tag memory means for storing the MSB portions of the virtual and physical addresses associated with said stored data, said stored virtual and physical MSB portions addressable by the received LSB portion for output from said tag memory means when said received LSB portion corresponds to the LSB portion of the address of the associated one of said stored data; arbitration means for selecting said stored virtual MSB portion if said received address is virtual and said physical MSB portion if said received address is physical; comparison means for comparing said received MSB portion with said selected MSB portion from said tag memory means; and switch means for outputting data from said cache memory means when a valid comparison is made by said comparison means.

Claim 3

The cache memory of Claim 1 and further comprising means for storing updated data in said cache memory means, the LSB portion of said updated data determining the address location in said cache memory means for storing said updated data; and

Claim 4

means for storing the MSB portion of the associated physical and virtual address of said updated data in an address location in said tag memory means determined by the LSB portion of the associated address of said updated data.

Claim 5

means for storing the MSB portion of the associated physical and virtual address of said updated data in an address location in said tag memory means determined by the LSB portion of the associated address of said updated data.

Claim 6

The cache memory of Claim 1 wherein said arbitration means comprises: an arbitration unit for receiving said address from said bus means and determining whether said address is a virtual address or a physical address, said arbitration unit generating a control signal at a first state in response to said received address being a virtual address and a second state in response to said address being a physical address; and a multiplex switch interfaced with the output of said tag memory means for selecting between said virtual MSB portion and said physical MSB portion output by said tag memory means, said multiplex switch controlled by said control signal from said arbitration unit to output said virtual MSB portion in response to said first state and said physical MSB portion in response to said second state, the output of said multiplex switch connected with the input of said comparison means.

Claim 7

The cache memory of Claim 1 wherein said comparison means comprises an exclusive OR circuit for receiving the MSB portion of said received address and the MSB portion output by said arbitration means, the output of said exclusive OR circuit controlling said switch means when the MSB portion of said received address is identical to the MSB portion selected by said arbitration means.

Claim 8

The cache memory of Claim 1 wherein the LSB portion of the virtual and physical address associated with data is divided into first and second fields and said cache memory means is divided into blocks of data, said first field defining the address location of said blocks of data and said second field defining the location of data within each of said blocks, said first portion of the LSB portion of the data address defining the location of said virtual and physical MSB portions of said stored data in said tag memory means.

Claim 9

The cache memory of Claim 1 wherein said tag memory means comprises first and second data memories each connected to the LSB portion of said bus means and having a plurality of memory locations therein, each addressable by the LSB portion of said received address such that data is output from each of said first and second memories for a given LSB portion of said received address, said first memory storing MSB portions of the physical address associated with data stored in said cache memory means and said second memory for storing the MSB portion of the physical address associated with data stored in said cache memory means, addressing of said first and second memory simultaneously outputting the virtual and physical MSB portions of data corresponding to the LSB portion of the said received address.

Claim 10

A cache memory addressable by both virtual and physical addresses, comprising: bus means for receiving an address from an external source representing desired data, addresses having an LSB portion and a tag portion, the LSB portion comprised of a predetermined number of the least significant bits of the address and the tag portion comprised of the remaining bits of the address, data being associated with both a physical and virtual address with the LSB portion of the virtual and physical addresses being identical; a cache data memory addressable by the LSB portion of said received address for storing select data therein at LSB address locations, said LSB address locations corresponding to the LSB portion of the address associated with said select data; a physical tag memory addressable by the LSB portion of said received address for storing the tag portion of the physical address associated with said select data at LSB address locations corresponding to the LSB portion of the stored physical tag portion; a virtual tag memory addressable by the LSB portion of said received address for storing the tag portion of the virtual address associated with said select data at LSB address locations corresponding to the LSB portion of the stored virtual tag portion; said cache memory outputting said select data in response to addressing by the LSB portion of said received address and said virtual and physical tag memories outputting the tag portion of the virtual and physical addresses corresponding to said select data output by said cache memory in response to addressing by the LSB portion of said received address; arbitration means connected to said bus means for determining whether said received address is a physical or a virtual address and outputting a control signal at a first state if said received address is virtual and at a second state if said received address is physical; multiplexer means controlled by said control signal and interfaced with said virtual and physical tag memories to output the virtual tag portion in response to said first state and the physical tag portion in response to said second state; a comparator for comparing the virtual or physical tag portion output by said multiplexer means with the tag portion of said received address; and a switch connected to the output of said cache memory and controlled by said comparator for outputting the address data of said cache memory when a true comparison is made by said comparator.

Claim 11

A cache memory addressable by both virtual and physical addresses, comprising: bus means for receiving an address from an external source representing desired data, addresses having an LSB portion and a tag portion, the LSB portion comprised of a predetermined number of the least significant bits of the address and the tag portion comprised of the remaining bits of the address, data being associated with both a physical and virtual address with the LSB portion of the virtual and physical addresses being identical; a cache data memory addressable by the LSB portion of said received address for storing select data therein at LSB address locations, said LSB address locations corresponding to the LSB portion of the address associated with said select data; a physical tag memory addressable by the LSB portion of said received address for storing the tag portion of the physical address associated with said select data at LSB address locations corresponding to the LSB portion of the stored physical tag portion; a virtual tag memory addressable by the LSB portion of said received address for storing the tag portion of the virtual address associated with said select data at LSB address locations corresponding to the LSB portion of the stored virtual tag portion; said cache memory outputting said select data in response to addressing by the LSB portion of said received address and said virtual and physical tag memories outputting the tag portion of the virtual and physical addresses corresponding to said select data output by said cache memory in response to addressing by the LSB portion of said received address; arbitration means connected to said bus means for determining whether said received address is a physical or a virtual address and outputting a control signal at a first state if said received address is virtual and at a second state if said received address is physical; multiplexer means controlled by said control signal and interfaced with said virtual and physical tag memories to output the virtual tag portion in response to said first state and the physical tag portion in response to said second state; a comparator for comparing the virtual or physical tag portion output by said multiplexer means with the tag portion of said received address; and a switch connected to the output of said cache memory and controlled by said comparator for outputting the address data of said cache memory when a true comparison is made by said comparator.

Claim 12

The cache memory of Claim 7 wherein said cache data memory is organized in blocks of data and the LSB portion of the address is divided into a first field and a second field, said first field defining the address location of each of said blocks of data and said second field defining the location of said data in each of said blocks, the tag portion of the associated address of said select data common to the addresses associated with all of select data in a given one of said blocks, said virtual and physical tag memories addressed by said first field of the LSB portion of said received address such that fewer tag portions are required to be stored in said virtual and physical tag memories.

Claim 13

The cache memory of Claim 7 wherein said comparator comprises an exclusive OR circuit.

Claim 14

The cache memory of Claim 7 and further comprising means for storing the virtual and physical tag portions of addresses associated with updated data that is stored in said cache data memory, said updated virtual and physical tag portions stored in address locations in said virtual and physical tag memories, respectively, associated with the LSB portions of the addresses associated with said updated data.

Claim 15

The cache memory of Claim 10 wherein said update means comprises: means for outputting both the virtual and tag portions of the address associated with said updated data in response to receiving either a virtual or a physical address, the tag portions of said virtual and physical addresses input to said multiplex means, said multiplex means being bidirectional to interface the virtual and physical tag portions associated with the update data to said virtual and physical tag memories for storage therein; and said arbitration unit controlling said multiplexer means to store the virtual tag portion in said virtual tag memory and the physical tag portion in said physical tag memory at an address location associated with the LSB portion of the associated address of said updated data.

Claim 18

The method of Claim 12 and further comprising storing the virtual and physical tag portions of update data when update data is stored in the cache data memory, the virtual and physical tag portions stored at an address location corresponding to the LSB portion of the update data.

Claim 19

The method of Claim 12 wherein the cache data memory is divided into blocks of data and the LSB portion of addresses divided into a first and a second field, the first field defining the blocks of data and the second field defining address locations within a selected block, the tag portion of the address associated with data stored in the cache memory identical for all data stored in a given one of the blocks, the tag portion addressed by the first field of the LSB portion.