US5884088A
Expired / Lapsed
US
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System, apparatus and method for managing power in a computer system
Assignee: Intel Corp
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Filing: 1997-07-10
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Granted: 1999-03-16
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Expires: 2017-07-10
Abstract
Abstract A computer system is provided for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.
Inventors
- 👤 James P. Kardach
- 👤 Chih-Hung Chung
- 👤 Jason Ziller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:29
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/3237; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
133 words
A computer system comprising: a processor having a bus controller (BC), said processor configured to provide indication of a beginning of a bus cycle; a bus activity monitor circuit (BAM), coupled to said BC, to provide indication of activity in said BC at least one clock cycle before said indication of beginning of a bus cycle is provided; a target controller (TC), coupled to said bus controller, to control exchange of information between said processor and a target circuit, said (TC) configured to receive control sequencing information; a power management circuit (PMC), to receive said indication of activity and, responsively, to provide said control sequencing information; and a resumption of activity circuit to provide said indication of a beginning of a bus cycle subsequent to a resumption of activity of said target controller.
Claim 2
Dependent Claim
133 words
A computer system comprising: a processor having a bus controller (BC), said processor configured to provide indication of a beginning of a bus cycle; a bus activity monitor circuit (BAM), coupled to said BC, to provide indication of activity in said BC at least one clock cycle before said indication of beginning of a bus cycle is provided; a target controller (TC), coupled to said bus controller, to control exchange of information between said processor and a target circuit, said (TC) configured to receive control sequencing information; a power management circuit (PMC), to receive said indication of activity and, responsively, to provide said control sequencing information; and a resumption of activity circuit to provide said indication of a beginning of a bus cycle subsequent to a resumption of activity of said target controller.
Claim 3
Dependent Claim
55 words
The computer system of claim 1 wherein said processor further includes a bus request queue to store addresses, said bus request queue having a first gate to receive a bus request (IBUSREQ) signal, said bus request queue having a second gate to generate a signal (BUSIDLE) indicative of an idle state of said bus controller.
Claim 4
Dependent Claim
46 words
The computer system of claim 2 wherein said bus activity monitor circuit has a first input, to receive said IBUSREQ signal, a second input, to receive said BUSIDLE signal, and an output to generate a bus activity signal providing said indication of activity in said BC.
Claim 5
Dependent Claim
25 words
The computer system of claim 1 wherein said indication of a beginning of a bus cycle is provided by way of an address valid signal.
Claim 6
Dependent Claim
36 words
The computer system of claim 3 wherein said bus activity monitor circuit includes an OR gate having a first input, to receive said IBUSREQ signal, a second input, to receive said BUSIDLE signal, and an output.
Claim 7
Dependent Claim
49 words
The computer system of claim 1 further including a bus interface, said bus interface including a second flip-flop latch having an input to receive said signal generated by said output of said bus activity monitor, said second flip-flop latch further including an output to generate said bus activity signal.
Claim 8
Dependent Claim
48 words
The computer system of claim 1 wherein said power management circuit includes an AND gate having a first input, to receive a signal indicating activity in said BC, a second input, to receive a clock signal, and an output to generate a signal providing said control sequencing information.
Claim 9
Dependent Claim
51 words
The computer system of claim 2 further including a second OR gate having a first input coupled to a DRAM refresh circuit, a second input coupled to said first bus queue, a third input coupled to said bus activity signal, and a fourth input coupled to a PCI clock control logic.
Claim 10
Dependent Claim
26 words
The computer system of claim 1 wherein said target controller is a dynamic random access memory (DRAM) controller and said target circuit is a DRAM memory.
Claim 11
Dependent Claim
61 words
A processor comprising: a bus controller coupled to a target controller, said bus controller including, a bus activity monitor circuit coupled to said bus controller to generate information indicative of activity in said bus controller, and a resumption of activity circuit to generate information, indicating the beginning of a bus cycle, subsequent to a resumption of activity of said target controller.
Claim 12
Dependent Claim
61 words
A processor comprising: a bus controller coupled to a target controller, said bus controller including, a bus activity monitor circuit coupled to said bus controller to generate information indicative of activity in said bus controller, and a resumption of activity circuit to generate information, indicating the beginning of a bus cycle, subsequent to a resumption of activity of said target controller.
Claim 13
Dependent Claim
25 words
The computer system of claim 10 wherein said indication of a beginning of a bus cycle is provided by way of an address valid signal.
Claim 14
Dependent Claim
42 words
The computer system of claim 10 further including a bus interface, that includes a second flip-flop latch having an input, to receive said signal generated by said output of said bus activity monitor, and an output to generate said bus activity signal.
Claim 15
Dependent Claim
49 words
The computer system of claim 10 wherein said power management circuit includes an AND gate having a first input, to receive a signal indicating activity in said BC, a second input, to receive a clock signal, and an output to generate a signal that provides said control sequencing information.
Claim 16
Dependent Claim
51 words
The computer system of claim 11 further including a second OR gate having a first input coupled to a DRAM refresh circuit, a second input coupled to said first bus queue, a third input coupled to said bus activity signal, and a fourth input coupled to a PCI clock control logic.
Claim 17
Dependent Claim
26 words
The computer system of claim 10 wherein said target controller includes a dynamic random access memory (DRAM) controller and said target circuit includes a DRAM memory.
References Cited (Backward Citations)
US4602327A
Cited
US5134691A
Cited
US5025387A
Cited
US5175845A
Cited
US5317750A
Cited
US5239638A
Cited
US5131083A
Cited
US5428790A
Cited
US5418969A
Cited
US5396635A
Cited
US5175853A
Cited
US5404546A
Cited
US5410711A
Cited
US5390350A
Cited
US5392417A
Cited
US5392023A
Cited
US5369771A
Cited
US5511205A
Cited
US5353420A
Cited
US5333307A
Cited
US5398244A
Cited
US5408668A
Cited
US5493684A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |