US5721935A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for entering low power mode in a computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-02-18
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Granted: 1998-02-24
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Expires: 2017-02-18
Abstract
Abstract A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
Inventors
- 👤 Todd J. DeSchepper
- 👤 James R. Reif
- 👤 James R. Edwards
- 👤 Michael J. Collins
- 👤 John E. Larson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:08
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3287; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
156 words
A method of managing power consumption in a computer system having a bus and having first and second power modes, the method performed by a bus device coupled to the bus, and the method comprising the steps of: detecting if the computer system is in the first power mode; determining if the bus device is granted control of the bus without requesting control of the bus; waiting for predetermined computer system activities to complete after it is detected that the computer system is in the first power mode and the bus device is granted control of the bus without requesting control of the bus; and transitioning the computer system from the first power mode to the second power mode after said predetermined computer system activities have completed and if the bus device is still granted control of the bus without requesting control of the bus and the computer system is still in the first power mode.
Claim 2
Independent Claim
156 words
A method of managing power consumption in a computer system having a bus and having first and second power modes, the method performed by a bus device coupled to the bus, and the method comprising the steps of: detecting if the computer system is in the first power mode; determining if the bus device is granted control of the bus without requesting control of the bus; waiting for predetermined computer system activities to complete after it is detected that the computer system is in the first power mode and the bus device is granted control of the bus without requesting control of the bus; and transitioning the computer system from the first power mode to the second power mode after said predetermined computer system activities have completed and if the bus device is still granted control of the bus without requesting control of the bus and the computer system is still in the first power mode.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein the computer system further includes a memory device which requires refresh cycles, and wherein said predetermined computer system activities include a memory refresh cycle.
Claim 4
Dependent Claim
15 words
The method of claim 1, wherein the bus is a preipheral component interface (PCI) bus.
Claim 5
Dependent Claim
65 words
The method of claim 3, wherein the computer system further includes a memory device which requires refresh cycles, wherein the computer system further includes a microprocessor coupled to a host bus, wherein the bus device is a processor-PCI bridge connected between said host bus and said PCI bus, and wherein said predetermined computer system activities include a memory refresh cycle and emptying a posting queue.
Claim 6
Dependent Claim
30 words
The method of claim 1, further comprising the step of: transitioning the computer system from the second power mode to the first power mode if the bus device becomes unparked.
Claim 7
Dependent Claim
64 words
The method of claim 1, wherein the first power mode is indicated if a first signal is asserted, and wherein said first signal continues to be asserted while the computer system is in the second power mode, the method further comprising the step of: transitioning the computer system from the second power mode to the first power mode if said first signal becomes deasserted.
Claim 8
Dependent Claim
35 words
The method of claim 6, wherein said second to first power mode transitioning step further transitions the computer system from the second power mode to the first power mode if the bus device becomes unparked.
Claim 9
Dependent Claim
27 words
The method of claim 1, wherein the first power mode is a first low power state and the second power mode is a second, lower power state.
Claim 10
Dependent Claim
181 words
A circuit for managing power consumption in a computer system having a bus and having first and second power modes, the circuit being located in a bus device coupled to the bus, the circuit comprising: a detector for detecting if the computer system is in the first power mode; an analyzer coupled to the bus for determining if the bus device is granted control of the bus without requesting control of the bus; a delay generator coupled to said detector and analyzer for waiting for predetermined computer system activities to complete after it is detected that the computer system is in the first power mode and the bus device is granted control of the bus without requesting control of the bus; and a controller coupled to said delay generator for transitioning the computer system from the first power mode to the second power mode after said predetermined computer system activities have completed and if the bus device is still granted control of the bus without requesting control of the bus and the computer system is still in the first power mode.
Claim 11
Dependent Claim
181 words
A circuit for managing power consumption in a computer system having a bus and having first and second power modes, the circuit being located in a bus device coupled to the bus, the circuit comprising: a detector for detecting if the computer system is in the first power mode; an analyzer coupled to the bus for determining if the bus device is granted control of the bus without requesting control of the bus; a delay generator coupled to said detector and analyzer for waiting for predetermined computer system activities to complete after it is detected that the computer system is in the first power mode and the bus device is granted control of the bus without requesting control of the bus; and a controller coupled to said delay generator for transitioning the computer system from the first power mode to the second power mode after said predetermined computer system activities have completed and if the bus device is still granted control of the bus without requesting control of the bus and the computer system is still in the first power mode.
Claim 12
Dependent Claim
30 words
The circuit of claim 9, wherein the computer system further includes a memory device which requires refresh cycles, and wherein said predetermined computer system activities include a memory refresh cycle.
Claim 13
Dependent Claim
15 words
The circuit of claim 9, wherein the bus is a peripheral component interface (PCI) bus.
Claim 14
Dependent Claim
36 words
The circuit of claim 11, wherein the computer system further has a microprocessor coupled to a host bus, and wherein the bus device is a processor-PCI bridge connected between said host bus and said PCI bus.
Claim 15
Dependent Claim
30 words
The circuit of claim 12, wherein the computer system further includes a memory device which requires refresh cycles, and wherein said predetermined computer system activities include a memory refresh cycle.
Claim 16
Dependent Claim
30 words
The circuit of claim 13, wherein said processor-PCI bridge includes a posting queue for posting bus cycles, and wherein said predetermined computer system activities further include emptying said posting queue.
Claim 17
Dependent Claim
26 words
The circuit of claim 9, wherein the first power mode is a fist low power state and second power mode is a second, lower power state.
Claim 18
Dependent Claim
34 words
The circuit of claim 9, further comprising: a sequencer coupled to said detector for transistioning the computer system from the second power mode to the first power mode if the bus device becomes unparked.
Claim 19
Dependent Claim
70 words
The circuit of claim 9, wherein the first power mode is indicated if a first signal is asserted, and wherein said first signal continues to be asserted while the computer system is in the second power mode, the circuit further comprising: a transition circuit responsive to said first signal for transitioning the computer system from the second power mode to the first power mode if said first signal becomes deasserted.
Claim 20
Dependent Claim
35 words
The circuit of claim 17, wherein said second to first power mode transition circuit further transitions the computer system from the second power mode to the first power mode if the bus device becomes unparked.
Claim 21
Dependent Claim
177 words
A computer system having first and second power modes, comprising: a bus; and a bus device coupled to said bus and including a power management circuit, said power management circuit comprising: a detector for detecting if the computer system is in the first power mode; an analyzer coupled to the bus for determining if the bus device is granted control of the bus without requesting control of the bus; a delay generator coupled to said detector and analyzer for waiting for predetermined computer system activities to complete after it is detected that the computer system is in the first power mode and the bus device is granted control of the bus without requesting control of the bus; and a controller coupled to said delay generator for transitioning the computer system from the first power mode to the second power mode after said predetermined computer system activities have completed and if the bus device is still granted control of the bus without requesting control of the bus and the computer system is still in the first power mode.
Claim 22
Dependent Claim
177 words
A computer system having first and second power modes, comprising: a bus; and a bus device coupled to said bus and including a power management circuit, said power management circuit comprising: a detector for detecting if the computer system is in the first power mode; an analyzer coupled to the bus for determining if the bus device is granted control of the bus without requesting control of the bus; a delay generator coupled to said detector and analyzer for waiting for predetermined computer system activities to complete after it is detected that the computer system is in the first power mode and the bus device is granted control of the bus without requesting control of the bus; and a controller coupled to said delay generator for transitioning the computer system from the first power mode to the second power mode after said predetermined computer system activities have completed and if the bus device is still granted control of the bus without requesting control of the bus and the computer system is still in the first power mode.
Claim 23
Dependent Claim
31 words
The computer system of claim 19, wherein the computer system further includes a memory device which requires refresh cycles, and wherein said predetermined computer system activities include a memory refresh cycle.
Claim 24
Dependent Claim
16 words
The computer system of claim 19, wherein said bus is a preipheral component interface (PCI) bus.
Claim 25
Dependent Claim
40 words
The computer system of claim 21, wherein the computer system further comprises: a host bus; a microprocessor coupled to said host bus, and wherein said bus device is a processor-PCI bridge connected between said host bus and said PCI bus.
Claim 26
Dependent Claim
31 words
The computer system of claim 22, wherein the computer system further includes a memory device which requires refresh cycles, and wherein said predetermined computer system activities include a memory refresh cycle.
Claim 27
Dependent Claim
31 words
The computer system of claim 23, wherein said processor-PCI bridge includes a posting queue for posting bus cycles, and wherein said predetermined computer system activities further include emptying said posting queue.
Claim 28
Dependent Claim
28 words
The computer system of claim 19, wherein the first power mode is a first low power state and the second power mode is a second, lower power state.
Claim 29
Dependent Claim
74 words
The computer system of claim 25, further comprising: a microprocessor coupled to said bus device; and a cache memory coupled to said microprocessor and said bus device, wherein said first low power state is a SLEEP -- state in which power consumption in said microprocessor is reduced, and wherein said second low power state is an IDLE state in which power consumption in said microprocessor, said cache memory, and said bus device is reduced.
Claim 30
Dependent Claim
40 words
The computer system of claim 19, wherein said power management circuit further comprises: a sequencer coupled to said detector for transitioning the computer system from the second power mode to the first power mode if the bus device becomes unparked.
Claim 31
Dependent Claim
74 words
The computer system of claim 19, wherein the first power mode is indicated if a first signal is asserted, wherein said first signal continues to be asserted while the computer system is in the second power mode, and wherein said power management circuit further comprises: a transition circuit responsive to said first signal for transitioning the computer system from the second power mode to the first power mode if said first signal becomes deasserted.
Claim 32
Dependent Claim
35 words
The circuit of claim 28, wherein said second to first power mode transition circuit further transitions the computer system from the second power mode to the first power mode if the bus device becomes unparked.
References Cited (Backward Citations)
US4317181A
Cited
US4980836A
Cited
US5167024A
Cited
US5396635A
Cited
US5404546A
Cited
US5475847A
Cited
US5504908A
Cited
US5586332A
Cited
US5493684A
Cited
US5517650A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |