US5740454A
Expired / Lapsed
US
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Circuit for setting computer system bus signals to predetermined states in low power mode
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1995-12-20
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Granted: 1998-04-14
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Expires: 2015-12-20
Abstract
Abstract A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STAND BY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.
Inventors
- 👤 Philip C. Kelly
- 👤 Todd J. DeSchepper
- 👤 James R. Reif
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:02
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3228
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
151 words
A circuit for managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the circuit comprising: means for detecting if the computer system is in the low power state; and means coupled to said detecting means for causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 2
Dependent Claim
151 words
A circuit for managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the circuit comprising: means for detecting if the computer system is in the low power state; and means coupled to said detecting means for causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 3
Dependent Claim
12 words
The circuit of claim 1, wherein the bus is a PCI bus.
Claim 4
Dependent Claim
18 words
The circuit of claim 2, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 5
Dependent Claim
20 words
The circuit of claim 3, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 6
Dependent Claim
36 words
The circuit of claim 2, wherein the computer system further includes a microprocessor coupled to a host bus, and wherein the first bus device is processor-PCI bridge connected between said host bus and said PCI bus.
Claim 7
Dependent Claim
25 words
The circuit of claim 1, wherein the first power supply voltage is about 3.3 volts and the second power supply voltage is about 5 volts.
Claim 8
Dependent Claim
12 words
The circuit of claim 6, wherein the bus is a PCI bus.
Claim 9
Dependent Claim
18 words
The circuit of claim 7, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 10
Dependent Claim
20 words
The circuit of claim 8, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 11
Dependent Claim
133 words
A computer system having at least one low power state, comprising: a bus having a plurality of bus signals; a first bus device coupled to said bus and operating off a first power supply voltage, wherein said first bus device has ownership of said bus in the low power state; a second bus device coupled to said bus and operating off a second power supply voltage, said second power supply voltage being greater than said first power supply voltage; and a power management circuit, comprising: means for detecting if the computer system is in the low power state; and means coupled to said detecting means for causing said first bus device to drive a portion of said bus signals to a zero state if the computer system is in the low power state.
Claim 12
Dependent Claim
133 words
A computer system having at least one low power state, comprising: a bus having a plurality of bus signals; a first bus device coupled to said bus and operating off a first power supply voltage, wherein said first bus device has ownership of said bus in the low power state; a second bus device coupled to said bus and operating off a second power supply voltage, said second power supply voltage being greater than said first power supply voltage; and a power management circuit, comprising: means for detecting if the computer system is in the low power state; and means coupled to said detecting means for causing said first bus device to drive a portion of said bus signals to a zero state if the computer system is in the low power state.
Claim 13
Dependent Claim
13 words
The computer system of claim 10, wherein said bus is a PCI bus.
Claim 14
Dependent Claim
19 words
The computer system of claim 11, wherein said bus signals driven to said zero state include PCI address/data signals.
Claim 15
Dependent Claim
21 words
The computer system of claim 12, wherein said bus signals driven to said zero state further include PCI byte enable signals.
Claim 16
Dependent Claim
38 words
The computer system of claim 11, wherein the computer system further includes a microprocessor coupled to a host bus, and wherein said first bus device : is processor-PCI bridge connected between said host bus and said PCI bus.
Claim 17
Dependent Claim
25 words
The computer system of claim 10, wherein said first power supply voltage-is about 3.3 volts and said second power supply voltage is about 5 volts.
Claim 18
Dependent Claim
13 words
The computer system of claim 15, wherein said bus is a PCI bus.
Claim 19
Dependent Claim
19 words
The computer system of claim 16, wherein said bus signals driven to said zero state include PCI address/data signals.
Claim 20
Dependent Claim
21 words
The computer system of claim 17, wherein said bus signals driven to said zero state further include PCI byte enable signals.
Claim 21
Independent Claim
145 words
A method of managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the method comprising the steps of: detecting if the computer system is in the low power state; and causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 22
Independent Claim
145 words
A method of managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the method comprising the steps of: detecting if the computer system is in the low power state; and causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 23
Dependent Claim
12 words
The method of claim 19, wherein the bus is a PCI bus.
Claim 24
Dependent Claim
18 words
The method of claim 20, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 25
Dependent Claim
20 words
The method of claim 21, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 26
Dependent Claim
25 words
The method of claim 19, wherein the first power supply voltage is about 3.3 volts and the second power supply voltage is about 5 volts.
Claim 27
Dependent Claim
12 words
The method of claim 23, wherein the bus is a PCI bus.
Claim 28
Dependent Claim
18 words
The method of claim 24, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 29
Dependent Claim
20 words
The method of claim 25, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 30
Dependent Claim
156 words
A circuit for managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the circuit comprising: a detection circuit for detecting if the computer system is in the low power state; and a signal driver circuit coupled to said detection circuit for causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 31
Dependent Claim
156 words
A circuit for managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the circuit comprising: a detection circuit for detecting if the computer system is in the low power state; and a signal driver circuit coupled to said detection circuit for causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 32
Dependent Claim
12 words
The circuit of claim 27, wherein the bus is a PCI bus.
Claim 33
Dependent Claim
18 words
The circuit of claim 28, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 34
Dependent Claim
20 words
The circuit of claim 29, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 35
Dependent Claim
36 words
The circuit of claim 28, wherein the computer system further includes a microprocessor coupled to a host bus, and wherein the first bus device is processor-PCI bridge connected between said host bus and said PCI bus.
Claim 36
Dependent Claim
25 words
The circuit of claim 27, wherein the first power supply voltage is about 3.3 volts and the second power supply voltage is about 5 volts.
Claim 37
Dependent Claim
12 words
The circuit of claim 32, wherein the bus is a PCI bus.
Claim 38
Dependent Claim
18 words
The circuit of claim 33, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 39
Dependent Claim
20 words
The circuit of claim 34, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 40
Dependent Claim
138 words
A computer system having at least one low power state, comprising: a bus having a plurality of bus signals; a first bus device coupled to said bus and operating off a first power supply voltage, wherein said first bus device has ownership of said bus in the low power state; a second bus device coupled to said bus and operating off a second power supply voltage, said second power supply voltage being greater than said first power supply voltage; and a power management circuit, comprising: a detection circuit for detecting if the computer system is in the low power state; and a signal driver circuit coupled to said detection circuit for causing said first bus device to drive a portion of said bus signals to a zero state if the computer system is in the low power state.
Claim 41
Dependent Claim
138 words
A computer system having at least one low power state, comprising: a bus having a plurality of bus signals; a first bus device coupled to said bus and operating off a first power supply voltage, wherein said first bus device has ownership of said bus in the low power state; a second bus device coupled to said bus and operating off a second power supply voltage, said second power supply voltage being greater than said first power supply voltage; and a power management circuit, comprising: a detection circuit for detecting if the computer system is in the low power state; and a signal driver circuit coupled to said detection circuit for causing said first bus device to drive a portion of said bus signals to a zero state if the computer system is in the low power state.
Claim 42
Dependent Claim
13 words
The computer system of claim 36, wherein said bus is a PCI bus.
Claim 43
Dependent Claim
19 words
The computer system of claim 37, wherein said bus signals driven to said zero state include PCI address/data signals.
Claim 44
Dependent Claim
21 words
The computer system of claim 38, wherein said bus signals driven to said zero state further include PCI byte enable signals.
Claim 45
Dependent Claim
37 words
The computer system of claim 37, wherein the computer system further includes a microprocessor coupled to a host bus, and wherein said first bus device is processor-PCI bridge connected between said host bus and said PCI bus.
Claim 46
Dependent Claim
26 words
The computer system of claim 36, wherein said first power supply voltage is about 3.3 volts and said second power supply voltage is about 5 volts.
Claim 47
Dependent Claim
13 words
The computer system of claim 41, wherein said bus is a PCI bus.
Claim 48
Dependent Claim
19 words
The computer system of claim 42, wherein said bus signals driven to said zero state include PCI address/data signals.
Claim 49
Dependent Claim
21 words
The computer system of claim 43, wherein said bus signals driven to said zero state further include PCI byte enable signals.
Claim 50
Independent Claim
145 words
A method of managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the method comprising the steps of: detecting if the computer system is in the low power state; and causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 51
Independent Claim
145 words
A method of managing power consumption in a computer system, the computer system having a bus and a first bus device and second bus device coupled to the bus, the bus having a plurality of bus signals, the first bus device operating off a first power supply voltage and the second bus device operating off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the method comprising the steps of: detecting if the computer system is in the low power state; and causing the first bus device to drive a portion of the bus signals to a zero state if the computer system is in the low power state.
Claim 52
Dependent Claim
12 words
The method of claim 45, wherein the bus is a PCI bus.
Claim 53
Dependent Claim
18 words
The method of claim 46, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 54
Dependent Claim
20 words
The method of claim 47, wherein the bus signals driven to said zero state further include PCI byte enable signals.
Claim 55
Dependent Claim
25 words
The method of claim 45, wherein the first power supply voltage is about 3.3 volts and the second power supply voltage is about 5 volts.
Claim 56
Dependent Claim
12 words
The method of claim 49, wherein the bus is a PCI bus.
Claim 57
Dependent Claim
18 words
The method of claim 50, wherein the bus signals driven to said zero state include PCI address/data signals.
Claim 58
Dependent Claim
20 words
The method of claim 51, wherein the bus signals driven to said zero state further include PCI byte enable signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-13 | 2001-10-13 | 2002-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-13 | 2005-10-13 | 2006-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-13 | 2009-10-13 | 2010-04-14 | $7700.00 | Window Closed / Lapsed |