US6968419B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory module having a memory module controller controlling memory transactions for a plurality of memory devices
Assignee: Intel Corp
•
Filing: 1998-02-13
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Granted: 2005-11-22
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Expires: 2018-02-13
Abstract
Abstract A memory module that has a plurality of memory devices and a memory module controller configured to receive a memory transaction from a first memory bus and to control access to the plurality of memory devices.
Inventors
- 👤 Thomas J. Holman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:47
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1694; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
58 words
A memory module, comprising: a memory module controller to communicate data between a system memory bus and a memory device regardless of any difference of signal impedance or operating voltage between the memory device and the system memory bus, memory module controller to receive a memory request signal from a system memory controller over the system memory bus.
Claim 2
Dependent Claim
58 words
A memory module, comprising: a memory module controller to communicate data between a system memory bus and a memory device regardless of any difference of signal impedance or operating voltage between the memory device and the system memory bus, memory module controller to receive a memory request signal from a system memory controller over the system memory bus.
Claim 3
Dependent Claim
48 words
The memory module of claim 1 , wherein the memory module controller further comprises a clock generator to generate a clock signal to drive separate signals addressed to and served by the memory device, wherein the clock signal is different than a clock signal of the memory bus.
Claim 4
Dependent Claim
52 words
The memory module of claim 2 , wherein the memory module controller further comprises a request handling logic to examine the memory request to determine whether the memory request is addressed to the memory device and to ignore the memory request if the memory request is not addressed to the memory device.
Claim 5
Dependent Claim
25 words
The memory of claim 3 , wherein the memory module controller further comprises a power management unit to control power supplied to the memory device.
Claim 6
Dependent Claim
20 words
The memory module of claim 4 , wherein the memory device and the memory bus operate at different power voltages.
Claim 7
Dependent Claim
35 words
The memory module of claim 4 , wherein the power management unit reduces at least a portion of the power to the memory device, if the memory request is not addressed to the memory device.
Claim 8
Dependent Claim
55 words
The memory module of claim 4 , wherein the memory module controller further comprises a control logic coupled to the request handling logic, the clock generator, and the power management unit, the control logic configured to decouple the memory device from the memory bus if the memory request is not addressed to the memory device.
Claim 9
Dependent Claim
49 words
The memory module of claim 7 , wherein in response to a signal from the request handling logic indicating that the memory request is not addressed to the memory device, the control logic instructs the clock generator to alter a frequency of the clock signal to the memory device.
Claim 10
Dependent Claim
45 words
The memory module of claim 8 , wherein the control logic further instructs the power management unit to disable the clock generator if the memory request is not addressed to of the memory device, which in turn reduces the power dissipation of the memory device.
Claim 11
Dependent Claim
37 words
The memory module of claim 1 , further comprising a bus interconnecting the plurality of memory device and the memory module controller, the bus having separate address, data, and control signal lines than the system memory bus.
Claim 12
Dependent Claim
18 words
The memory module of claim 1 , wherein the memory module is a dual inline memory module (DIMM).
Claim 13
Dependent Claim
18 words
The memory module of claim 1 , wherein the memory module is a single inline memory module (SIMM).
Claim 14
Dependent Claim
21 words
The memory module of claim 1 , wherein the memory device comprises one of volatile memory devices and non-volatile memory devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-11-21 | 2009-05-23 | 2009-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-11-21 | 2013-05-23 | 2013-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-11-21 | 2017-05-23 | 2017-11-22 | $7700.00 | Window Closed / Lapsed |