US5883839A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Waveform stabilizing drive circuit for modularized memory
Assignee: Fujitsu Ltd
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Filing: 1997-10-07
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Granted: 1999-03-16
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Expires: 2017-10-07
Abstract
Abstract A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive signal from the memory controller and transmitting the received drive signal to the memory module. Signal reflection noises produced in the memory module are absorbed by the buffer.
Inventors
- 👤 Masaki Tosaka
- 👤 Yuzo Usui
- 👤 Noriyuki Matsui
- 👤 Masao Matsuda
- 👤 Kazunori Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C5/00; G11C5/06; G11C5/063; G11C7/00; G11C7/22; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
72 words
A memory drive circuit comprising: a memory module including a plurality of memory elements; a memory controller driving said memory module; and a buffer, disposed between said memory module and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to said memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module.
Claim 2
Dependent Claim
72 words
A memory drive circuit comprising: a memory module including a plurality of memory elements; a memory controller driving said memory module; and a buffer, disposed between said memory module and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to said memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module.
Claim 3
Dependent Claim
75 words
A memory drive circuit according to claim 1, wherein: said memory module has an impedance in a predetermined range of impedances; the impedance of the conductor connecting said buffer to said memory module is set to a value falling within the predetermined range of impedances; and a transition time of the signal output from said buffer is set coincident to or larger than a time for which the signal is propagated through said memory module.
Claim 4
Dependent Claim
103 words
A memory drive circuit comprising: a memory module including a plurality of memory elements; a memory controller driving said memory module; and a buffer, disposed between said memory module and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to said memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module; and wherein the impedance of the conductor connecting said buffer to said memory module is set to a value falling within a range of impedances that said memory module can take.
Claim 5
Dependent Claim
103 words
A memory drive circuit comprising: a memory module including a plurality of memory elements; a memory controller driving said memory module; and a buffer, disposed between said memory module and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to said memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module; and wherein the impedance of the conductor connecting said buffer to said memory module is set to a value falling within a range of impedances that said memory module can take.
Claim 6
Dependent Claim
38 words
A memory drive circuit according to claim 3, wherein a transition time of the signal output from said buffer is set coincident to or larger than a time for which the signal is propagated through said memory module.
Claim 7
Dependent Claim
103 words
A memory drive circuit comprising: a memory module including a plurality of memory elements; a memory controller driving said memory module; and a buffer, disposed between said memory module and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to said memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module; and wherein a transition time of the signal output from said buffer is set coincident to or larger than a time for which the signal is propagated through said memory module.
Claim 8
Dependent Claim
103 words
A memory drive circuit comprising: a memory module including a plurality of memory elements; a memory controller driving said memory module; and a buffer, disposed between said memory module and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to said memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module; and wherein a transition time of the signal output from said buffer is set coincident to or larger than a time for which the signal is propagated through said memory module.
Claim 9
Dependent Claim
75 words
A memory drive circuit comprising: at least one connector to which a memory module is to be connected; a memory controller driving the memory module; and a buffer, disposed between said connector and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to the memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module.
Claim 10
Dependent Claim
75 words
A memory drive circuit comprising: at least one connector to which a memory module is to be connected; a memory controller driving the memory module; and a buffer, disposed between said connector and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to the memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to said memory module.
Claim 11
Dependent Claim
68 words
A memory drive circuit according to claim 6, wherein the impedance of the conductor connecting said buffer to the memory module is set to a value falling within a range of impedances that the memory module can take, and a transition time of the signal output from said buffer is set coincident to or larger than a time for which the signal is propagated through the memory module.
Claim 12
Dependent Claim
104 words
A memory drive circuit comprising: a connector to which a memory module is to be connected; a memory controller driving the memory module; and a buffer, disposed between said connector and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to the memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to the memory module; and wherein the impedance of the conductor connecting said buffer to the memory module is set to a value falling within a range of impedances that the memory module can take.
Claim 13
Dependent Claim
104 words
A memory drive circuit comprising: a connector to which a memory module is to be connected; a memory controller driving the memory module; and a buffer, disposed between said connector and said memory controller, receiving a drive signal from said memory controller and transmitting the received drive signal to the memory module, an output impedance of said buffer being matched to an impedance of a conductor connecting said buffer to the memory module; and wherein the impedance of the conductor connecting said buffer to the memory module is set to a value falling within a range of impedances that the memory module can take.
Claim 14
Dependent Claim
38 words
A memory drive circuit according to claim 8, wherein a transition time of the signal output from said buffer is set coincident to or larger than a time for which the signal is propagated through the memory module.
References Cited (Backward Citations)
JPH0325993A
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JPH0462895A
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JPH05143535A
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US5729764A
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JPH09214076A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |