US7045396B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stackable semiconductor package and method for manufacturing same
Assignee: Amkor Technology Singapore Holding Pte Ltd
•
Filing: 2003-05-16
•
Granted: 2006-05-16
•
Expires: 2023-05-16
Abstract
Abstract Leadframe-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.
Inventors
- 👤 Sean Timothy Crowley
- 👤 Angel Orabuena Alvarez
- 👤 Jun Young Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:24
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W70/00; H10W70/40; H10W70/421; H10W70/424; H10W70/427; H10W90/00; H10W70/60; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/721; H10W90/722; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
185 words
A method of fabricating a semiconductor package, comprising the steps of: a) providing a leadframe comprising: a die paddle defining opposed, generally planar top and bottom surfaces; and a plurality of leads extending at least partially about the die paddle in spaced relation thereto, each of the leads having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions; the transition from the first end to the second end in each of the leads occurring without the lower portion reversing direction to extend along the upper portion; b) attaching a semiconductor chip to the top surface of the die paddle; c) electrically connecting the semiconductor chip to at least one of the leads; and d) at least partially encapsulating the leadframe and the semiconductor chip with a sealing material such that the bottom sides of the lower portions of the leads and the top sides of the upper portions of the leads are exposed in the sealing material.
Claim 2
Independent Claim
185 words
A method of fabricating a semiconductor package, comprising the steps of: a) providing a leadframe comprising: a die paddle defining opposed, generally planar top and bottom surfaces; and a plurality of leads extending at least partially about the die paddle in spaced relation thereto, each of the leads having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions; the transition from the first end to the second end in each of the leads occurring without the lower portion reversing direction to extend along the upper portion; b) attaching a semiconductor chip to the top surface of the die paddle; c) electrically connecting the semiconductor chip to at least one of the leads; and d) at least partially encapsulating the leadframe and the semiconductor chip with a sealing material such that the bottom sides of the lower portions of the leads and the top sides of the upper portions of the leads are exposed in the sealing material.
Claim 3
Dependent Claim
41 words
The method of claim 1 wherein: step (c) comprises electrically connecting the semiconductor chip to the lower portion of at least one of the leads via a conductive wire; and step (d) comprises encapsulating the conductive wire with the sealing material.
Claim 4
Dependent Claim
45 words
The method of claim 2 wherein step (c) comprises connecting the conductive wire to a bond side of the lower portion which is disposed in opposed relation to the bottom side and extends in generally co-planar relation to the top surface of the die paddle.
Claim 5
Dependent Claim
28 words
The method of claim 1 wherein step (d) comprises partially encapsulating the leadframe such that the bottom surface of the die paddle is exposed in the sealing material.
Claim 6
Dependent Claim
27 words
The method of claim 4 wherein step (d) comprises filling the sealing material into a notched portion which extends about the bottom surface of the die paddle.
Claim 7
Dependent Claim
29 words
The method of claim 1 wherein step (d) comprises filling the sealing material into an etched portion formed within the upper and lower portions of each of the leads.
Claim 8
Dependent Claim
69 words
The method of claim 1 further comprising the steps of: e) attaching a top section to the top side of the upper section of each of the leads such that the top section protrudes outwardly from the sealing material; and f) attaching a bottom section to the bottom side of the lower section of each of the leads such that the bottom section protrudes outwardly from the sealing material.
Claim 9
Dependent Claim
47 words
The method of claim 7 wherein: step (e) comprises attaching a solder plate to the top side of the upper section of each of the leads; and step (f) comprises attaching a solder plate to the bottom side of the lower section of each of the leads.
Claim 10
Independent Claim
236 words
A method of fabricating a semiconductor package, comprising the steps of: a) providing a leadframe comprising: a die paddle defining opposed, generally planar top and bottom surfaces; a first set of leads extending at least partially about the die paddle in spaced relation thereto; and a second set of leads extending at least partially about the leads of the first set in spaced relation thereto, each of the leads of the first and second sets having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions, the transition from the first end to the second end in each of the leads of the first and second sets occuring without the lower portion reversing direction to extend along the upper portion; b) attaching a semiconductor chip to the top surface of the die paddle; c) electrically connecting the semiconductor chip to at least one of the leads of each of the first and second sets; and d) partially encapsulating the leadframe and the semiconductor chip with a sealing material such that the bottom sides of the lower portions of the leads of the first and second sets and the top sides of the upper portions of the leads of the first and second sets are exposed in the sealing material.
Claim 11
Independent Claim
236 words
A method of fabricating a semiconductor package, comprising the steps of: a) providing a leadframe comprising: a die paddle defining opposed, generally planar top and bottom surfaces; a first set of leads extending at least partially about the die paddle in spaced relation thereto; and a second set of leads extending at least partially about the leads of the first set in spaced relation thereto, each of the leads of the first and second sets having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions, the transition from the first end to the second end in each of the leads of the first and second sets occuring without the lower portion reversing direction to extend along the upper portion; b) attaching a semiconductor chip to the top surface of the die paddle; c) electrically connecting the semiconductor chip to at least one of the leads of each of the first and second sets; and d) partially encapsulating the leadframe and the semiconductor chip with a sealing material such that the bottom sides of the lower portions of the leads of the first and second sets and the top sides of the upper portions of the leads of the first and second sets are exposed in the sealing material.
Claim 12
Dependent Claim
48 words
The method of claim 9 wherein: step (c) comprises electrically connecting the semiconductor chip to the lower portion of at least one of the leads of each of the first and second sets via conductive wires; and step (d) comprises encapsulating the conductive wires with the sealing material.
Claim 13
Dependent Claim
47 words
The method of claim 10 wherein step (c) comprises connecting each of the conductive wires to a bond side of the lower portion which is disposed in opposed relation to the bottom side and extends in generally co-planar relation to the top surface of the die paddle.
Claim 14
Dependent Claim
32 words
The method of claim 9 wherein step (d) comprises partially encapsulating the leadframe with the sealing material such that the bottom surface of the die paddle is exposed in the sealing material.
Claim 15
Dependent Claim
27 words
The method of claim 12 wherein step (d) comprises filling the sealing material into a notched portion which extends about the bottom surface of the die paddle.
Claim 16
Dependent Claim
37 words
The method of claim 9 wherein step (d) comprises filling the sealing material into an etched portion formed in the upper and lower portions of each of the leads of each of the first and second sets.
Claim 17
Dependent Claim
84 words
The method of claim 9 further comprising the steps of: e) attaching a top section to the top side of the upper section of each of the leads of the first and second sets such that each of the top sections protrudes outwardly from the sealing material; and attaching a bottom section to the bottom side of the lower section of each of the leads of the first and second sets such that each of the bottom sections protrudes outwardly from the sealing material.
Claim 18
Dependent Claim
59 words
The method of claim 15 wherein: step (e) comprises attaching a solder plate to the top side of the upper section of each of the leads of the first and second sets; and step (f) comprises attaching a solder plate to the bottom side of the lower section of each of the leads of the first and second sets.
Claim 19
Independent Claim
217 words
A method of fabricating a chip stack, comprising the steps of: a) providing first and second semiconductor packages, each of which comprises: a die paddle defining opposed, generally planar top and bottom surfaces; a plurality of leads extending at least partially about the die paddle in spaced relation thereto, each of the leads having an upper portion defining a generally planar top side and first end, a lower portion defining a generally planar bottom side, and a middle portion extending between the upper and lower portions, the transition from the first end to the second end in each of the leads occurring without the lower portion reversing direction to extend along the upper portion; a semiconductor chip attached to the top surface of the die paddle and electrically connected to at least one of the leads; and a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom sides of the lower portions of the leads and the top sides of the upper portions of the leads are exposed in the sealing material; and b) electrically connecting the top sides of the upper portions of the leads of the first semiconductor package to respective ones of the top sides of the upper portions of the leads of the second semiconductor package.
Claim 20
Independent Claim
217 words
A method of fabricating a chip stack, comprising the steps of: a) providing first and second semiconductor packages, each of which comprises: a die paddle defining opposed, generally planar top and bottom surfaces; a plurality of leads extending at least partially about the die paddle in spaced relation thereto, each of the leads having an upper portion defining a generally planar top side and first end, a lower portion defining a generally planar bottom side, and a middle portion extending between the upper and lower portions, the transition from the first end to the second end in each of the leads occurring without the lower portion reversing direction to extend along the upper portion; a semiconductor chip attached to the top surface of the die paddle and electrically connected to at least one of the leads; and a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom sides of the lower portions of the leads and the top sides of the upper portions of the leads are exposed in the sealing material; and b) electrically connecting the top sides of the upper portions of the leads of the first semiconductor package to respective ones of the top sides of the upper portions of the leads of the second semiconductor package.
Claim 21
Dependent Claim
37 words
The method of claim 17 further comprising the step of: c) electrically connecting a third semiconductor package to the bottom sides of the lower portions of the leads of one of the first and second semiconductor packages.
Claim 22
Independent Claim
328 words
A method of fabricating a chip stack, comprising the steps of: a) providing first and second semiconductor packages, each of which comprises: a die paddle defining opposed, generally planar top and bottom surfaces; a first set of leads extending at least partially about the die paddle in spaced relation thereto; a second set of leads extending at least partially about the leads of the first set in spaced relation thereto, each of the leads of the first and second sets having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions the transition from the first end to the second end in each of the leads of the first and second sets occurring without the lower portion reversing direction to extend along the upper portion; a semiconductor chip attached to the top surface of the die paddle and electrically connected to at least one of the leads of each of the first and second sets; and a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom sides of the lower portions of the leads of the first and second sets and the top sides of the upper portions of the leads of the first and second sets are exposed in the sealing material; b) electrically connecting the bottom sides of the lower portions of the leads of the first set of the first semiconductor package to respective ones of the bottom sides of the lower portions of the leads of the first set of the second semiconductor package; and c) electrically connecting the bottom sides of the lower portions of the leads of the second set of the first semiconductor package to respective ones of the bottom sides of the lower portions of the leads of the second set of the second semiconductor package.
Claim 23
Independent Claim
328 words
A method of fabricating a chip stack, comprising the steps of: a) providing first and second semiconductor packages, each of which comprises: a die paddle defining opposed, generally planar top and bottom surfaces; a first set of leads extending at least partially about the die paddle in spaced relation thereto; a second set of leads extending at least partially about the leads of the first set in spaced relation thereto, each of the leads of the first and second sets having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions the transition from the first end to the second end in each of the leads of the first and second sets occurring without the lower portion reversing direction to extend along the upper portion; a semiconductor chip attached to the top surface of the die paddle and electrically connected to at least one of the leads of each of the first and second sets; and a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom sides of the lower portions of the leads of the first and second sets and the top sides of the upper portions of the leads of the first and second sets are exposed in the sealing material; b) electrically connecting the bottom sides of the lower portions of the leads of the first set of the first semiconductor package to respective ones of the bottom sides of the lower portions of the leads of the first set of the second semiconductor package; and c) electrically connecting the bottom sides of the lower portions of the leads of the second set of the first semiconductor package to respective ones of the bottom sides of the lower portions of the leads of the second set of the second semiconductor package.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-05-15 | 2009-11-14 | 2010-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-05-15 | 2013-11-14 | 2014-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-05-15 | 2017-11-14 | 2018-05-16 | $7700.00 | Window Closed / Lapsed |