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US4907067A Expired / Lapsed US ⏱️ 0.0 years remaining

Thermally efficient power device package

Assignee: Texas Instruments Inc
•
Filing: 1988-05-11
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Granted: 1990-03-06
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Expires: 2008-05-11
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Abstract

Abstract A hermetic semiconductor device package is disclosed which is capable of handling high power devices in an electrically and thermally efficient manner. The package includes a dielectric substrate with cutouts for die mount and/or bonding to a plurality of thermally and electrically conductive plates which are electrically isolated from each other.

Inventors

  • 👤 Lesli A. Derryberry

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 09:11
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W76/60; H10W72/00; H10W72/90; H10W72/931; H10W72/932

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 72 words
A high current, thermally efficient semiconductor device package, comprising; a plurality of metal base plates, and electrically insulating substrate mounted on and bonded to said metal base plates, and an enclosure for mounting on said electrically insulating substrate and enclosing such semiconductor device that is mounted on said electrically insulating substrate, the metal base plates being adapted for electrical interconnection to the semiconductor device that is mounted on the electrically insulating substrate.
Claim 2
Dependent Claim 72 words
A high current, thermally efficient semiconductor device package, comprising; a plurality of metal base plates, and electrically insulating substrate mounted on and bonded to said metal base plates, and an enclosure for mounting on said electrically insulating substrate and enclosing such semiconductor device that is mounted on said electrically insulating substrate, the metal base plates being adapted for electrical interconnection to the semiconductor device that is mounted on the electrically insulating substrate.
Claim 3
Dependent Claim 63 words
The device package according to claim 1, wherein said metal base plates have opposed sides and wherein said electrically insulating substrate is mounted on and bonded to one of said sides of said metal base plates, further comprising: a dielectric layer bonded to the other one of said sides of said metal base plates to isolate the metal plates from a mounting surface.
Claim 4
Dependent Claim 35 words
The package according to claim 1, wherein said electrically insulating substrate has a plurality of openings therein to allow interconnecting between a semiconductor device mounted on said electrically insulating substrate and said metal base plates.
Claim 5
Dependent Claim 31 words
The package according to claim 1, further comprising: electrically conductive connection pads on one side of said metal plates to permit surface mounting of the package to a printed circuit board.
Claim 6
Dependent Claim 27 words
The package according to claim 1, further comprising: lateral extensions on each of said metal plates to permit screw mounting of said package to a circuit board.
Claim 7
Dependent Claim 20 words
The package according to claim 1, wherein said metal plates are electrically isolated from each other by a sealing material.
Claim 8
Dependent Claim 117 words
A package for a thermally efficient power semiconductor device, comprising; a dielectric substrate for mounting a semiconductor device, a plurality of thermally and electrically conductive plates electrically isolated from each other and physically arranged to provide connection to a semiconductor device, and to provide current carrying capacity and thermal dissipation for a semiconductor device, said conductive plates having opposed sides, said dielectric substrate mounted on and bonded to one of said sides of said conductive plates, an enclosure for hermetically enclosing a semiconductor device mounted on said dielectric substrate, and connection terminals for electrically contacting said conductive plates for providing external connections to a semiconductor device mounted on said dielectric substrate and hermetically sealed within said package.
Claim 9
Dependent Claim 117 words
A package for a thermally efficient power semiconductor device, comprising; a dielectric substrate for mounting a semiconductor device, a plurality of thermally and electrically conductive plates electrically isolated from each other and physically arranged to provide connection to a semiconductor device, and to provide current carrying capacity and thermal dissipation for a semiconductor device, said conductive plates having opposed sides, said dielectric substrate mounted on and bonded to one of said sides of said conductive plates, an enclosure for hermetically enclosing a semiconductor device mounted on said dielectric substrate, and connection terminals for electrically contacting said conductive plates for providing external connections to a semiconductor device mounted on said dielectric substrate and hermetically sealed within said package.
Claim 10
Dependent Claim 31 words
The device package according to claim 7, including a dielectric layer bonded to the other one of said sides of said conductive plates to isolate said plates from a mounting surface.
Claim 11
Dependent Claim 32 words
The package according to claim 7, wherein said dielectric substrate has a plurality of openings therein to allow interconnection between a semiconductor device mounted on said dielectric substrate and said conductive plates.
Claim 12
Dependent Claim 29 words
The package according to claim 7, including electrically conductive connection pads on one side of said conductive plates to permit surface mounting of the package to a circuit board.
Claim 13
Dependent Claim 26 words
The package according to claim 7, including lateral extensions on each of said conductive plates to permit screw mounting of said package to a circuit board.
Claim 14
Dependent Claim 20 words
The package according to claim 7, wherein said conductive plates are electrically isolated from each other by a sealing material.

References Cited (Backward Citations)

US3025437A Cited
WO1979000302A1 Cited
JPS57107063A Cited
DE3125360A1 Cited
JPS60180130A Cited
US4698662A Cited
US4703339A Cited
JPS63133555A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-03-05 1993-09-04 1994-03-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-03-05 1997-09-04 1998-03-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-03-05 2001-09-04 2002-03-06 $7700.00 Window Closed / Lapsed

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