Method of making plastic encapsulated multichip hybrid integrated circuits

Claim 1

A method of making a hybrid integrated circuit, comprising the steps of: (a) forming a metal layer pattern on a surface of an insulative film, the metal layer pattern including a plurality of individual bonding strips, a flag area, and a plating bus connected to the bonding strips and the flag area; (b) electroplating a metal coating onto the metal layer pattern while applying an electroplating voltage to the plating bus; (c) punching a piece out of the insulative film so as to produce a cutout larger than a first integrated circuit chip and so that the piece contains the bonding strips and the flag area and no interconnected parts of the plating bus are on the piece; (d) attaching the piece to a first area of a flag of a lead frame to partially cover the flag of the lead frame while leaving uncovered a second area of the flag of the lead frame, the second area being exposed through the cutout, the lead frame having a plurality of fingers; (e) die bonding the first integrated circuit chip to the second area of the flag of the lead frame, and die bonding a second integrated circuit to the flag area; (f) wire bonding each of a plurality of bonding pads of the first and second integrated circuit chips to various bonding strips, respectively, and wire bonding some of the bonding strips to various fingers of the lead frame, respectively, and wire bonding each of the bonding strips located along an edge of the cutout to both a bonding pad on the first integrated circuit chip and to a corresponding bonding pad on the second integrated circuit chip, respectively, the first integrated circuit being a relatively high power dissipation integrated circuit, and the second integrated circuit being a relatively low power dissipation integrated circuit; and (g) filling a volume containing the bonding wires, the first and second integrated circuit chips, and the flag and fingers of the lead frame with plastic to plastic-encapsulate the hybrid integrated circuit.

Claim 2

A method of making a hybrid integrated circuit, comprising the steps of: (a) forming a metal layer pattern on a surface of an insulative film, the metal layer pattern including a plurality of individual bonding strips, a flag area, and a plating bus connected to the bonding strips and the flag area; (b) electroplating a metal coating onto the metal layer pattern while applying an electroplating voltage to the plating bus; (c) punching a piece out of the insulative film so as to produce a cutout larger than a first integrated circuit chip and so that the piece contains the bonding strips and the flag area and no interconnected parts of the plating bus are on the piece; (d) attaching the piece to a first area of a flag of a lead frame to partially cover the flag of the lead frame while leaving uncovered a second area of the flag of the lead frame, the second area being exposed through the cutout, the lead frame having a plurality of fingers; (e) die bonding the first integrated circuit chip to the second area of the flag of the lead frame, and die bonding a second integrated circuit to the flag area; (f) wire bonding each of a plurality of bonding pads of the first and second integrated circuit chips to various bonding strips, respectively, and wire bonding some of the bonding strips to various fingers of the lead frame, respectively, and wire bonding each of the bonding strips located along an edge of the cutout to both a bonding pad on the first integrated circuit chip and to a corresponding bonding pad on the second integrated circuit chip, respectively, the first integrated circuit being a relatively high power dissipation integrated circuit, and the second integrated circuit being a relatively low power dissipation integrated circuit; and (g) filling a volume containing the bonding wires, the first and second integrated circuit chips, and the flag and fingers of the lead frame with plastic to plastic-encapsulate the hybrid integrated circuit.

Claim 3

A method of making a hybrid integrated circuit, comprising the steps of: (a) forming a metal layer pattern on a surface of an insulative film, the metal layer pattern including a plurality of individual bonding strips, a flag area, and a plating bus connected to the bonding strips and the flag area, the insulative film being in the form of an elongated ribbon having therein first and second groups of sprocket receiving holes located along opposed edges of portions of the insulative film, respectively; (b) electroplating a metal coating onto the metal layer pattern while applying an electroplating voltage to the plating bus; (c) punching a piece out of the insulative film so as to produce a cutout larger than a first integrated circuit chip and so that the piece contains the bonding strips and the flag area and no interconnected parts of the plating bus are on the piece; (d) advancing the insulative film by means of a sprocketed spool and the sprocket receiving holes to align a portion of the insulative film with a punch; (e) attaching the piece to a first area of a flag of a lead frame to partially cover the flag of the lead frame while leaving uncovered a second area of the flag of the lead frame, the second area being exposed through the cutout, the lead frame having a plurality of fingers; (f) die bonding the first integrated circuit chip to the second area of the flag of the lead frame, and die bonding a second integrated circuit to the flag area; (g) wire bonding each of a plurality of bonding pads of the first and second integrated circuit chips to various bonding strips, respectively, and wire bonding some of the bonding strips to various fingers of the lead frame, respectively, and wire bonding each of the bonding strips located along an edge of the cutout to both a bonding pad on the first integrated circuit chip and to a corresponding bonding pad on the second integrated circuit chip, respectively, the first integrated circuit being a relatively high power dissipation integrated circuit, and the second integrated circuit being a relatively low power dissipation integrated circuit; and (h) filling a volume containing the bonding wires, the first integrated circuit chip, and the flag and fingers of the lead frame with plastic to plastic-encapsulate the hybrid integrated circuit.

Claim 4

A method of making a hybrid integrated circuit, comprising the steps of: (a) forming a metal layer pattern on a surface of an insulative film, the metal layer pattern including a plurality of individual bonding strips, a flag area, and a plating bus connected to the bonding strips and the flag area, the insulative film being in the form of an elongated ribbon having therein first and second groups of sprocket receiving holes located along opposed edges of portions of the insulative film, respectively; (b) electroplating a metal coating onto the metal layer pattern while applying an electroplating voltage to the plating bus; (c) punching a piece out of the insulative film so as to produce a cutout larger than a first integrated circuit chip and so that the piece contains the bonding strips and the flag area and no interconnected parts of the plating bus are on the piece; (d) advancing the insulative film by means of a sprocketed spool and the sprocket receiving holes to align a portion of the insulative film with a punch; (e) attaching the piece to a first area of a flag of a lead frame to partially cover the flag of the lead frame while leaving uncovered a second area of the flag of the lead frame, the second area being exposed through the cutout, the lead frame having a plurality of fingers; (f) die bonding the first integrated circuit chip to the second area of the flag of the lead frame, and die bonding a second integrated circuit to the flag area; (g) wire bonding each of a plurality of bonding pads of the first and second integrated circuit chips to various bonding strips, respectively, and wire bonding some of the bonding strips to various fingers of the lead frame, respectively, and wire bonding each of the bonding strips located along an edge of the cutout to both a bonding pad on the first integrated circuit chip and to a corresponding bonding pad on the second integrated circuit chip, respectively, the first integrated circuit being a relatively high power dissipation integrated circuit, and the second integrated circuit being a relatively low power dissipation integrated circuit; and (h) filling a volume containing the bonding wires, the first integrated circuit chip, and the flag and fingers of the lead frame with plastic to plastic-encapsulate the hybrid integrated circuit.