Packaged semiconductor device

Claim 1

A semiconductor device, comprising: a semiconductor chip; a substrate having an upper major surface, and a lower major surface for supporting the semiconductor chip on the upper major surface thereof; a plurality of terminals provided on the substrate for external connection, said plurality of terminals being provided to project from the lower major surface of the substrate; a plurality of lead wires provided on the semiconductor chip for electrical connection to the plurality of terminals; and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip, said multilevel interconnection structure including a lower conductor layer having an upper major surface, and a lower major surface provided on the upper major surface of the substrate, said lower conductor layer being patterned into a plurality of isolated patterns each surrounded by a boundary and connected electrically to at least one terminals, said plurality of isolated patterns exposing a part of the upper major surface of the substrate therebetween; an insulator layer having an upper major surface, and a lower major surface provided on the lower conductor layer such that the lower major surface of the insulator layer covers the upper major surface of the lower conductor layer an the exposed part of the upper major surface of the substrate, said upper major surface of the insulator layer forming a depression corresponding to the exposed part of the upper major surface of the substrate; a plurality of contact holes provided in the insulator layer for exposing the upper major surface of the lower conductor layer corresponding to the isolated patterns; and an upper conductor layer having an upper major surface, and a lower major surface provided on the upper major surface of the insulator layer, said upper conductor layer being patterned into a plurality of conductor strips each extending from a corresponding contact hole and connected to a corresponding isolated pattern at the contact hole, each conductor strip having a straight portion that extends parallel with each other corresponding to the plurality of lead wires for electrical connection therewith; wherein certain of said isolated patterns have their boundary crossing the straight portions of the conductor strips and said certain isolated patterns are formed such that the boundary forms a liner edge that extends general linerarly in the plane of the upper major surface of the substrate and crosses, when viewed perpendicularly to the upper major surface of the substrate, the straight portions generally obliquely, said linear edge being formed to cross a plurality of the conductor strips.