US5592025A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pad array semiconductor device
Assignee: NXP USA Inc
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Filing: 1994-12-05
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Granted: 1997-01-07
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Expires: 2014-12-05
Abstract
Abstract Pad array carriers allow greater I/O densities over conventional leaded packages by using an array arrangement for external electrical connections. A pad array carrier (48) is manufactured using a substrate (40) having metal on only one side and unplated through-holes (44). A semiconductor die (50) is mounted on and affixed to the top surface of the substrate with an electrically insulative adhesive (51). The use of the insulative adhesive allows routing of signal traces into the die mounting region directly underneath the die. Wire bonds (52) connect the die to metal traces (46) on the substrate. A package body (54) is formed on the substrate covering the die and wire bonds (52). Solder balls (56 & 58) are directly attached to the backside of the solder pads (47) by way of the through-holes.
Inventors
- 👤 Minh-Hien N. Clark
- 👤 James W. Sloan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:50
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W90/00; H10W90/701; H05K2201/00; H05K2201/03; H05K2201/0302; H05K2201/0305; H05K2201/0332; H05K2201/0388; H05K2201/0394; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09472; H05K3/40; H05K3/4038; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/071; H10W72/073; H10W72/07351; H10W72/07353; H10W72/075; H10W72/07551; H10W72/07554; H10W72/20; H10W72/29; H10W72/30; H10W72/331; H10W72/334; H10W72/50; H10W72/541; H10W72/5449; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W90/731; H10W90/734; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
142 words
A pad array semiconductor device comprising: a substrate having a die mounting region on a first surface, a second surface, and a plurality of through-holes, only the first surface having a pattern of conductive metal traces which includes a plurality of solder pads overlying the plurality of through-holes, wherein the plurality of solder pads is larger in diameter than the plurality of through-holes; a semiconductor die mounted on and directly affixed to the first surface of the substrate in the die mounting region with an electrically insulative adhesive; a plurality of wire bonds electrically connecting the semiconductor die to the pattern of conductive metal traces; a package body formed by an encapsulating material covering the semiconductor die and the plurality of wire bonds; and a plurality of solder balls directly attached to the plurality of solder pads through the plurality of through-holes.
Claim 2
Dependent Claim
142 words
A pad array semiconductor device comprising: a substrate having a die mounting region on a first surface, a second surface, and a plurality of through-holes, only the first surface having a pattern of conductive metal traces which includes a plurality of solder pads overlying the plurality of through-holes, wherein the plurality of solder pads is larger in diameter than the plurality of through-holes; a semiconductor die mounted on and directly affixed to the first surface of the substrate in the die mounting region with an electrically insulative adhesive; a plurality of wire bonds electrically connecting the semiconductor die to the pattern of conductive metal traces; a package body formed by an encapsulating material covering the semiconductor die and the plurality of wire bonds; and a plurality of solder balls directly attached to the plurality of solder pads through the plurality of through-holes.
Claim 3
Dependent Claim
19 words
The semiconductor device of claim 1, wherein the encapsulating material forming the package body is a polymeric molding compound.
Claim 4
Dependent Claim
34 words
The semiconductor device of claim 1, wherein the pattern of conductive metal traces extend into the die mounting region, wherein a portion of the metal traces in the die mounting region comprises signal traces.
Claim 5
Dependent Claim
31 words
The semiconductor device of claim 1, wherein the substrate is composed of a material selected from a group consisting of: polyester reinforced with glass fibers and polyimide reinforced with glass fibers.
Claim 6
Dependent Claim
22 words
The semiconductor device of claim 4, wherein the substrate has a thickness substantially in a range of 0.1 millimeter to 0.2 millimeter.
Claim 7
Dependent Claim
19 words
The semiconductor device of claim 1, wherein the electrically insulative adhesive is an epoxy resin filled with aluminum oxide.
Claim 8
Dependent Claim
41 words
The semiconductor device of claim 1, wherein the substrate has a first coefficient of thermal expansion and the encapsulating material has a second coefficient of thermal expansion, the first and second coefficients of thermal expansion being substantially in a same range.
Claim 9
Dependent Claim
156 words
A semiconductor device comprising: a substrate having a die mounting region on a first surface, a second surface, and a plurality of unplated through-holes, only the first surface having a pattern of conductive metal traces which includes a plurality of solder pads overlying the plurality of through-holes, wherein the plurality of solder pads is larger in diameter than the plurality of through-holes, the substrate having a thickness substantially in a range of 0.1 millimeter to 0.2 millimeter; a semiconductor die mounted on and directly affixed to the first surface of the substrate in the die mounting region with an electrically insulative adhesive; a plurality of wire bonds electrically connecting the semiconductor die to the pattern of conductive metal traces; a package body formed by an encapsulating material covering the semiconductor die and the plurality of wire bonds; and a plurality of solder balls directly attached to the plurality of solder pads through the plurality of through-holes.
Claim 10
Dependent Claim
156 words
A semiconductor device comprising: a substrate having a die mounting region on a first surface, a second surface, and a plurality of unplated through-holes, only the first surface having a pattern of conductive metal traces which includes a plurality of solder pads overlying the plurality of through-holes, wherein the plurality of solder pads is larger in diameter than the plurality of through-holes, the substrate having a thickness substantially in a range of 0.1 millimeter to 0.2 millimeter; a semiconductor die mounted on and directly affixed to the first surface of the substrate in the die mounting region with an electrically insulative adhesive; a plurality of wire bonds electrically connecting the semiconductor die to the pattern of conductive metal traces; a package body formed by an encapsulating material covering the semiconductor die and the plurality of wire bonds; and a plurality of solder balls directly attached to the plurality of solder pads through the plurality of through-holes.
Claim 11
Dependent Claim
20 words
The semiconductor device of claim 8, wherein the package body is either a molded package body or a glob top.
Claim 12
Dependent Claim
39 words
The semiconductor device of claim 8, wherein the pattern of conductive metal traces extend into the die mounting region, wherein a portion of the metal traces in the die mounting region comprises signal traces and a central ground pad.
Claim 13
Dependent Claim
31 words
The semiconductor device of claim 8, wherein the substrate is composed of a material selected from a group consisting of: polyester reinforced with glass fibers and polyimide reinforced with glass fibers.
Claim 14
Dependent Claim
19 words
The semiconductor device of claim 8, wherein the electrically insulative adhesive is an epoxy resin filled with aluminum oxide.
Claim 15
Dependent Claim
41 words
The semiconductor device of claim 8, wherein the substrate has a first coefficient of thermal expansion and the encapsulating material has a second coefficient of thermal expansion, the first and second coefficients of thermal expansion being substantially in a same range.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |