US6166991A
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US
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Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
Assignee: Carmel Semiconductor LLC
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Filing: 1999-11-03
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Granted: 2000-12-26
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Expires: 2019-11-03
Abstract
Abstract An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.
Inventors
- 👤 Cathal Phelan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:34
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
53 words
An apparatus comprising: a first circuit configured to generate (i) one or more internal select signals and (ii) a control signal in response to one or more chip select signals; and a second circuit configured to automatically generate a sleep signal in response to (i) said control signal and (ii) a clock signal.
Claim 2
Independent Claim
53 words
An apparatus comprising: a first circuit configured to generate (i) one or more internal select signals and (ii) a control signal in response to one or more chip select signals; and a second circuit configured to automatically generate a sleep signal in response to (i) said control signal and (ii) a clock signal.
Claim 3
Dependent Claim
19 words
The apparatus according to claim 1, wherein said one or more chip select signals comprise a chip enable signal.
Claim 4
Dependent Claim
23 words
The apparatus according to claim 1, wherein said one or more internal select signals correspond to said one or more chip select signals.
Claim 5
Dependent Claim
16 words
The apparatus according to claim 1, wherein said circuit is part of a synchronous integrated circuit.
Claim 6
Dependent Claim
14 words
The apparatus according to claim 1, wherein said first circuit is an input buffer.
Claim 7
Dependent Claim
13 words
The apparatus according to claim 5, wherein said second circuit is a counter.
Claim 8
Dependent Claim
14 words
The apparatus according to claim 4, wherein said synchronous integrated circuit is an SRAM.
Claim 9
Dependent Claim
18 words
The apparatus according to claim 4, wherein said synchronous integrated circuit is an application specific integrated circuit (ASIC).
Claim 10
Dependent Claim
15 words
The apparatus according to claim 1, wherein said clock signal is an external clock signal.
Claim 11
Dependent Claim
15 words
The apparatus according to claim 1, wherein said clock signal is an internal clock signal.
Claim 12
Dependent Claim
15 words
The apparatus according to claim 1, wherein said sleep signal is a Jedec-standard "ZZ" signal.
Claim 13
Dependent Claim
20 words
The apparatus according to claim 1, wherein said second circuit is enabled or disabled in response to an enable signal.
Claim 14
Dependent Claim
46 words
A circuit comprising: means for generating (i) a control signal and (ii) one or more internal select signals in response to one or more chip select signals; and means for generating a sleep signal in response to (i) said control signal and (ii) a clock signal.
Claim 15
Dependent Claim
46 words
A circuit comprising: means for generating (i) a control signal and (ii) one or more internal select signals in response to one or more chip select signals; and means for generating a sleep signal in response to (i) said control signal and (ii) a clock signal.
Claim 16
Independent Claim
56 words
A method for reducing power consumption in a synchronous integrated circuit comprising the steps of: (A) generating (i) a control signal and (ii) one or more internal select signals in response to one or more chip select signals; and (B) generating a sleep signal in response to (i) said control signal and (ii) a clock signal.
Claim 17
Independent Claim
56 words
A method for reducing power consumption in a synchronous integrated circuit comprising the steps of: (A) generating (i) a control signal and (ii) one or more internal select signals in response to one or more chip select signals; and (B) generating a sleep signal in response to (i) said control signal and (ii) a clock signal.
Claim 18
Dependent Claim
14 words
The method according to claim 14, wherein said synchronous integrated circuit is an SRAM.
Claim 19
Dependent Claim
15 words
The method according to claim 14, wherein said clock signal is an external clock signal.
Claim 20
Dependent Claim
15 words
The method according to claim 14, wherein said clock signal is an internal clock signal.
Claim 21
Dependent Claim
79 words
The method according to claim 14, wherein step B comprises the sub-steps of: (B-1) when said control signal is in a first state, counting a number of pulses of said clock signal; (B-2) when said number of pulses counted reaches a predetermined value, setting said sleep signal to a first state; and (B-3) when said control signal is in a second state, (i) resetting said number of pulses counted and/or (ii) setting said sleep signal to a second state.
Claim 22
Dependent Claim
12 words
The method according to claim 18, wherein said predetermined value is programmable.
Claim 23
Dependent Claim
15 words
The method according to claim 13, wherein said sleep signal is a Jedec-standard "ZZ" signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |