US6363031B2
Expired / Lapsed
US
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Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
Assignee: Powerwatch Systems LLC
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Filing: 2000-12-22
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Granted: 2002-03-26
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Expires: 2020-12-22
Abstract
Abstract An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.
Inventors
- 👤 Cathal Phelan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:46
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
47 words
An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles, wherein said circuit is enabled or disabled in response to an enable signal.
Claim 2
Independent Claim
47 words
An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles, wherein said circuit is enabled or disabled in response to an enable signal.
Claim 3
Dependent Claim
35 words
The apparatus according to claim 1 , wherein said circuit comprises: an input buffer configured to generate a control signal; and a counter configured to generate said sleep signal in response to said control signal.
Claim 4
Dependent Claim
16 words
The apparatus according to claim 1 , wherein said sleep signal is a Jedec-standard “ZZ” signal.
Claim 5
Dependent Claim
21 words
The apparatus according to claim 1 , wherein said circuit is further configured to generate one or more internal select signals.
Claim 6
Dependent Claim
24 words
The apparatus according to claim 4 , wherein said one or more internal select signals correspond to said one or more chip select signals.
Claim 7
Dependent Claim
17 words
The apparatus according to claim 1 , wherein said circuit is part of a synchronous integrated circuit.
Claim 8
Dependent Claim
15 words
The apparatus according to claim 6 , wherein said synchronous integrated circuit comprises an SRAM.
Claim 9
Dependent Claim
19 words
The apparatus according to claim 6 , wherein said synchronous integrated circuit comprises an application specific integrated circuit (ASIC).
Claim 10
Dependent Claim
17 words
The apparatus according to claim 1 , wherein said circuit is further responsive to a clock signal.
Claim 11
Dependent Claim
21 words
The apparatus according to claim 9 , wherein said clock signal comprises an internal clock signal or an external clock signal.
Claim 12
Independent Claim
66 words
A method for reducing power consumption in a synchronous integrated circuit comprising the steps of: (A) detecting if one or more chip select signals has been in a first state for a predetermined number of clock cycles; and (B) automatically generating a Jedec-standard “ZZ” signal when said one or more chip select signals has been in said first state for said predetermined number of clock cycles.
Claim 13
Independent Claim
66 words
A method for reducing power consumption in a synchronous integrated circuit comprising the steps of: (A) detecting if one or more chip select signals has been in a first state for a predetermined number of clock cycles; and (B) automatically generating a Jedec-standard “ZZ” signal when said one or more chip select signals has been in said first state for said predetermined number of clock cycles.
Claim 14
Dependent Claim
28 words
The method according to claim 11 , wherein step (B) further comprises: generating one or more internal select signals corresponding to said one or more chip set signgnals.
Claim 15
Dependent Claim
21 words
The method according to claim 11 , wherein said Jedec-standard “ZZ” signal is automatically generated in response to a clock signal.
Claim 16
Dependent Claim
79 words
The method according to claim 13 , further comprising the sub-steps of: when a control signal is in a first state, counting a number of pulses of said clock signal; when said number of pulses counted reaches a predetermined value, setting said Jedec-standard “ZZ” signal to a first predetermined state; and when said control signal is in a second state, (i) resetting said number of pulses counted and/or (ii) setting said Jedec-standard “ZZ” signal to a second predetermined state.
Claim 17
Independent Claim
35 words
An apparatus comprising a circuit configured to automatically generate a Jedec-standard “ZZ” signal upon detecting that one or more chip select signals have been in a first state for a predetermined number of clock cycles.
Claim 18
Independent Claim
35 words
An apparatus comprising a circuit configured to automatically generate a Jedec-standard “ZZ” signal upon detecting that one or more chip select signals have been in a first state for a predetermined number of clock cycles.
Claim 19
Dependent Claim
22 words
The apparatus according to claim 15 , wherein each of said one or more chip select signals comprise a chip enable signal.
Claim 20
Dependent Claim
20 words
The apparatus according to claim 15 , wherein said circuit is enabled or disabled in response to an enable signal.
Claim 21
Dependent Claim
21 words
The apparatus according to claim 15 , wherein said circuit is further configured to generate one or more internal select signals.
Claim 22
Dependent Claim
17 words
The apparatus according to claim 15 , wherein said circuit is further responsive to a clock signal.
Claim 23
Dependent Claim
21 words
The apparatus according to claim 19 , wherein said clock signal comprises an internal clock signal or an external clock signal.
Claim 24
Independent Claim
81 words
A method for reducing power consumption in a synchronous integrated circuit comprising the steps of: counting a number of pulses of said clock signal when a control signal is in a first state; when said number of pulses counted reaches a predetermined value, automatically setting a sleep signal to a first predetermined state; and when said control signal is in a second state, (i) resetting said number of pulses counted and/or (ii) setting said sleep signal to a second predetermined state.
Claim 25
Independent Claim
81 words
A method for reducing power consumption in a synchronous integrated circuit comprising the steps of: counting a number of pulses of said clock signal when a control signal is in a first state; when said number of pulses counted reaches a predetermined value, automatically setting a sleep signal to a first predetermined state; and when said control signal is in a second state, (i) resetting said number of pulses counted and/or (ii) setting said sleep signal to a second predetermined state.
Claim 26
Dependent Claim
15 words
The method according to claim 21 , wherein said synchronous integrated circuit comprises an SRAM.
Claim 27
Dependent Claim
13 words
The method according to claim 21 , wherein said predetermined value is programmable.
Claim 28
Dependent Claim
16 words
The method according to claim 21 , wherein said sleep signal comprises a Jedec-standard “ZZ” signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-03-25 | 2005-09-24 | 2006-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-25 | 2009-09-24 | 2010-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-25 | 2013-09-24 | 2014-03-26 | $7700.00 | Window Closed / Lapsed |