US5935255A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CPU core to bus speed ratio detection
Assignee: Rambus Inc
•
Filing: 1996-02-23
•
Granted: 1999-08-10
•
Expires: 2016-02-23
Abstract
Abstract A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system using the CPU itself, rather than an external agent, to sample the external pins on RESET and latch their core/bus frequency ratio information into an internal register. By accessing the information in this internal register, it is possible for the BIOS or any other software to read the internal to external clock ratios and optimize the performance of the system.
Inventors
- 👤 K. C. So
- 👤 Rajesh Manapat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:04
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G06F11/00; G06F11/30; G06F11/3003; G06F11/3024; G06F11/3051; G06F11/22; G06F11/2205; G06F11/221; G06F11/2289; G06F11/34; G06F11/3466; G06F11/348
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
70 words
A method for determining a CPU's core-to-bus frequency ratio in a computer system, comprising the steps of: asserting a reset signal; sampling, with said CPU, at least one pin external to the CPU while said reset signal is asserted to obtain core-to-bus frequency ratio information; latching said information into a register in said CPU; and accessing said information in said register by one or more components in said computer system.
Claim 2
Independent Claim
70 words
A method for determining a CPU's core-to-bus frequency ratio in a computer system, comprising the steps of: asserting a reset signal; sampling, with said CPU, at least one pin external to the CPU while said reset signal is asserted to obtain core-to-bus frequency ratio information; latching said information into a register in said CPU; and accessing said information in said register by one or more components in said computer system.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein said latching step is performed in the falling edge of the reset signal.
Claim 4
Dependent Claim
11 words
The method of claim 2 wherein said register comprises a flip-flop.
Claim 5
Dependent Claim
18 words
The method of claim 3 wherein said reset signal is coupled to said flip-flip circuit by a buffer.
Claim 6
Dependent Claim
18 words
The method of claim 1 wherein said accessing step comprises storing and retrieving an instruction from said register.
Claim 7
Dependent Claim
17 words
The method of claim 5 wherein said instruction comprises a software instruction in a computer readable medium.
Claim 8
Dependent Claim
19 words
The method of claim 5 wherein said accessing step comprises providing said core-to-bus frequency ratio to a system BIOS.
Claim 9
Dependent Claim
76 words
A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system, comprising: means for asserting a reset signal; means on said CPU for sampling at least one pin external to the CPU while said reset signal is asserted, said pin providing core-to-bus frequency ratio information; means in said CPU for storing said ratio information; and means for accessing said ratio information in said storage means by one or more components in said computer system.
Claim 10
Dependent Claim
76 words
A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system, comprising: means for asserting a reset signal; means on said CPU for sampling at least one pin external to the CPU while said reset signal is asserted, said pin providing core-to-bus frequency ratio information; means in said CPU for storing said ratio information; and means for accessing said ratio information in said storage means by one or more components in said computer system.
Claim 11
Dependent Claim
12 words
The mechanism of claim 8 wherein said storage means comprises a flip-flop.
Claim 12
Dependent Claim
24 words
The mechanism of claim 8 wherein said latching means latches said ratio information into said register on a falling edge of said reset signal.
Claim 13
Dependent Claim
18 words
The mechanism of claim 9 further comprising a buffer for coupling said reset signal and said flip-flop circuit.
Claim 14
Dependent Claim
12 words
The mechanism of claim 8 wherein said ratio comprises a CPU instruction.
Claim 15
Dependent Claim
16 words
The mechanism of claim 8 wherein said ratio comprises at least part of a system instruction.
Claim 16
Dependent Claim
14 words
The mechanism of claim 8 wherein said ratio comprises one or more system instructions.
Claim 17
Dependent Claim
29 words
The method of claim 14 wherein said accessing means comprises means for using said one or more system instructions to provide said core-to-bus frequency ratio to a system BIOS.
Claim 18
Dependent Claim
97 words
A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system, comprising: a first circuit configured to assert a reset signal; an access point on said CPU for sampling at least one external pin while said reset signal is asserted, said at least one external pin providing core-to-bus frequency ratio information; a register in said CPU for storing said ratio information; a latch circuit, coordinated with said reset signal for latching said ratio information into said register; and a second circuit for accessing said ratio information in said register by components in said computer system.
Claim 19
Dependent Claim
97 words
A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system, comprising: a first circuit configured to assert a reset signal; an access point on said CPU for sampling at least one external pin while said reset signal is asserted, said at least one external pin providing core-to-bus frequency ratio information; a register in said CPU for storing said ratio information; a latch circuit, coordinated with said reset signal for latching said ratio information into said register; and a second circuit for accessing said ratio information in said register by components in said computer system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |