US6233192B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Sharp Corp
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Filing: 1999-03-05
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Granted: 2001-05-15
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Expires: 2019-03-05
Abstract
Abstract The present invention is to provide a method for designating a memory bank to be refreshed efficiently and a start and termination procedure of a self-refresh. In a dynamic RAM including a plurality of memory banks 200 A, 200 B, memory access actions being allowed to be independently on the respective memory banks, and a refresh control circuit for allowing the plurality of memory banks 200 A, 200 B to be refreshed in a lump and for allowing one memory bank 200 A or 200 B of the plurality of memory banks designated to be refreshed, a semiconductor memory device is configured such that when a row address input terminal or one of specific input terminals other than the row address input terminal is at a high level, the plurality of memory banks are refreshed in a lump; and when the row address input terminal or one of specific input terminals other than the row address input terminal is at a low level, one of the plurality of memory banks is designated to be refreshed in accordance with a bank selecting bit composed of one bit or a combination of a plurality of bits of row addresses other than the row address.
Inventors
- 👤 Hidehiko Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
174 words
A semiconductor memory device comprising: a plurality of memory banks, memory access actions being allowed to be independently performed on the respective memory banks; and a refresh control circuit for allowing the plurality of memory banks to be refreshed in a lump and for allowing one or more memory banks of the plurality of memory banks designated to be refreshed, the semiconductor memory device being a dynamic random access memory, wherein when a specific input terminal is at a first level, the plurality of memory banks are refreshed in a lump, and when the specific input terminal is at a second level, one of the plurality of memory banks is designated to be refreshed in accordance with a bank selecting bit composed of one bit or a combination of a plurality of bits inputted from terminals other than the specific input terminal, wherein the semiconductor device is configured so that a memory bank address-storing mode register need not be referred to for at least one of the plurality of memory banks to be refreshed.
Claim 2
Dependent Claim
174 words
A semiconductor memory device comprising: a plurality of memory banks, memory access actions being allowed to be independently performed on the respective memory banks; and a refresh control circuit for allowing the plurality of memory banks to be refreshed in a lump and for allowing one or more memory banks of the plurality of memory banks designated to be refreshed, the semiconductor memory device being a dynamic random access memory, wherein when a specific input terminal is at a first level, the plurality of memory banks are refreshed in a lump, and when the specific input terminal is at a second level, one of the plurality of memory banks is designated to be refreshed in accordance with a bank selecting bit composed of one bit or a combination of a plurality of bits inputted from terminals other than the specific input terminal, wherein the semiconductor device is configured so that a memory bank address-storing mode register need not be referred to for at least one of the plurality of memory banks to be refreshed.
Claim 3
Dependent Claim
196 words
A semiconductor memory device comprising: a plurality of memory banks, memory access actions being allowed to be independently performed on the respective memory banks; and a refresh control circuit for allowing the plurality of memory banks to be refreshed in a lump and for allowing one or more memory banks of the plurality of memory banks designated to be refreshed, the semiconductor memory device being a dynamic random access memory, wherein when one of a row address input terminal and a specific input terminal other than the row address input terminal is at a high level, the plurality of memory banks are refreshed in a lump, and when one of the row address input terminal and the specific input terminal is at a low level, one of the plurality of memory banks is designated to be refreshed in accordance with a bank selecting bit composed of one bit or a combination of a plurality of bits of row addresses other than the row address, wherein the semiconductor device is configured so that a memory bank address-storing mode register need not be referred to for at least one of the plurality of memory banks to be refreshed.
Claim 4
Dependent Claim
196 words
A semiconductor memory device comprising: a plurality of memory banks, memory access actions being allowed to be independently performed on the respective memory banks; and a refresh control circuit for allowing the plurality of memory banks to be refreshed in a lump and for allowing one or more memory banks of the plurality of memory banks designated to be refreshed, the semiconductor memory device being a dynamic random access memory, wherein when one of a row address input terminal and a specific input terminal other than the row address input terminal is at a high level, the plurality of memory banks are refreshed in a lump, and when one of the row address input terminal and the specific input terminal is at a low level, one of the plurality of memory banks is designated to be refreshed in accordance with a bank selecting bit composed of one bit or a combination of a plurality of bits of row addresses other than the row address, wherein the semiconductor device is configured so that a memory bank address-storing mode register need not be referred to for at least one of the plurality of memory banks to be refreshed.
Claim 5
Dependent Claim
79 words
The semiconductor memory device of claim 2 , wherein synchronously with a rising of a clock signal CLK, a chip selecting signal /CS, a row address strobe signal /RAS and a column address strobe signal /CAS are set at low levels, and a write enable signal /WE and a clock enable signal CKE are set at high levels, so that a designation of a bank to be auto-refreshed is made possible by inputting an address signal at that time.
Claim 6
Dependent Claim
79 words
The semiconductor memory device of claim 2 , wherein synchronously with a rising of a clock signal CLK, a chip selecting signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a clock enable signal CKE are set at low levels, and a write enable signal /WE is set at a high level, so that a designation of a bank to be self-refreshed is made possible by inputting an address signal at that time.
Claim 7
Dependent Claim
84 words
The semiconductor memory device of claim 4 , wherein synchronously with the rising of the clock signal CLK, the chip selecting signal /CS, the row address strobe signal /RAS and the write enable signal /WE are set at low levels, and the column address strobe signal /CAS and the clock enable signal CKE are set at high levels, so that a designation of a bank, the auto-refresh of which is to be terminated, is made possible by inputting an address signal at that time.
Claim 8
Dependent Claim
84 words
The semiconductor memory device of claim 4 , wherein synchronously with the rising of the clock signal CLK, the chip selecting signal /CS, the row address strobe signal /RAS, the column address strobe signal /CAS, and the clock enable signal CKE are set at low levels, and the write enable signal /WE is set at a high level, so that a designation of a bank, the self-refresh of which is to be terminated, is made possible by inputting an address signal at that time.
Claim 9
Dependent Claim
77 words
The semiconductor memory device of claim 4 , wherein synchronously with the rising of the clock signal CLK, the chip selecting signal /CS, the row address strobe signal /RAS, the column address strobe signal /CAS, the write enable signal /WE and the clock enable signal CKE are set at low levels, so that a designation of a bank, the self-refresh of which is to be terminated, is made possible by inputting an address signal at that time.
Claim 10
Dependent Claim
84 words
The semiconductor memory device of claim 4 , wherein synchronously with the rising of the clock signal CLK, the chip selecting signal /CS and the write enable signal /WE are set at low levels and the row address strobe signal /RAS, the column address strobe signal /CAS and the clock enable signal CKE are set at high levels, so that a designation of a bank, the self-refresh of which is to be terminated, is made possible by inputting an address signal at that time.
Claim 11
Dependent Claim
31 words
The semiconductor memory device of claim 2 , wherein during a memory bank being refreshed, a read action is performed on a column address in a bank which is not refreshed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-14 | 2004-11-13 | 2005-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-14 | 2008-11-13 | 2009-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-14 | 2012-11-13 | 2013-05-15 | $7700.00 | Window Closed / Lapsed |