DRAM having self-timed burst refresh mode

Claim 3

The method of claim 1 wherein the step of providing addresses from the internal counter further includes employing a variable row select function to select more rows for refreshing than in a normal mode of operation of the memory circuit so that each active cycle refreshes more rows than are normally refreshed in normal mode.

Claim 4

The method of claim 1 wherein said step of entering burst refresh mode includes detecting a set of prescribed conditions on one or more inputs to said memory circuit.

Claim 5

The method of claim 3 wherein said detecting step includes detecting said prescribed conditions among an address bit, a column address signal and a write enable signal.

Claim 6

The method of claim 1 wherein said step of self-timing the active cycle includes: detecting the condition of an electrical signal used during a sensing operation associated with said refreshing, and determining whether said electrical signal has reached a predetermined condition.

Claim 7

The method of claim 5 wherein said memory circuit uses a latch signal to latch sense amplifiers within the memory circuit, and wherein said condition is a voltage level of said latch signal.

Claim 8

The method of claim 6 wherein said latch signal is a latch signal for activating p-channel transistors in sense amplifiers of the memory circuit.

Claim 9

The method of claim 1 wherein said precharge cycle is associated with a clock signal, and wherein said step of self-timing the precharge cycle includes interposing a delay based on said clock signal.

Claim 10

The method of claim 8 wherein said clock signal includes a shorting clock signal, and wherein said step of self-timing the precharge cycle includes receiving said shorting clock signal and providing a delayed shorting clock signal based thereon.

Claim 11

The method of claim 1 including counting the number of burst refresh mode cycles so that all of said rows of the memory circuit are refreshed.

Claim 12

The method of claim 1 further comprising generating a burst refresh mode finished signal when all of the rows have been refreshed.

Claim 15

The method of claim 12 wherein said step of repeating includes indexing a count of rows that have been refreshed and terminating said burst refresh mode when all of the rows have been refreshed.

Claim 16

The method of claim 13 wherein said step of indexing includes counting the number of times said auto-refresh signal is generated.

Claim 19

The method of claim 15 wherein said self-timing includes self-timing at least a selected one of an active cycle and a precharge cycle for each row being refreshed.

Claim 20

The method of claim 16 wherein said self-timing includes self-timing both the active cycle and the precharge cycle for each row being refreshed, including internally detecting when said refreshing of a row is substantially completed.

Claim 23

The method of claim 18 further comprising generating a burst refresh mode finished signal when all of the rows have been refreshed.

Claim 24

A memory circuit comprising: a plurality of memory cells arranged in rows and columns; a plurality of sense amplifiers coupled to said columns of memory cells; a sense amplifier driver circuit coupled to said plurality of sense amplifiers; a control signal circuit (102) coupled to receive an externally-applied control signal(/RAS); a refresh counter circuit (106); a plurality of address buffers coupled to said control signal circuit and said refresh counter circuit; a row decoder circuit coupled to said address buffers and to said rows of memory cells; a precharge and clock circuit responsively coupled to said control signal circuit for providing a precharge signal used to precharge the sense amplifiers; a detector circuit (126) coupled to said sense amplifier driver circuit to provide a refresh finished (RF) signal indicative that a refresh cycle is substantially completed; a burst refresh mode control circuit (134, 140) coupled to receive externally-applied signals and effective for determining whether the memory circuit should enter burst refresh mode; and a selectively operable burst refresh mode circuit (132) responsively coupled to said burst refresh mode control circuit, the burst refresh mode circuit being coupled to said control signal circuit (102) and coupled to receive said refresh finished signal (RF) from said detector circuit (126), said burst refresh mode circuit being effective to cause said memory circuit to generate successive addresses for refreshing rows of memory cells in response to successive ones of said refresh finished signal (RF).

Claim 25

A memory circuit comprising: a plurality of memory cells arranged in rows and columns; a plurality of sense amplifiers coupled to said columns of memory cells; a sense amplifier driver circuit coupled to said plurality of sense amplifiers; a control signal circuit (102) coupled to receive an externally-applied control signal(/RAS); a refresh counter circuit (106); a plurality of address buffers coupled to said control signal circuit and said refresh counter circuit; a row decoder circuit coupled to said address buffers and to said rows of memory cells; a precharge and clock circuit responsively coupled to said control signal circuit for providing a precharge signal used to precharge the sense amplifiers; a detector circuit (126) coupled to said sense amplifier driver circuit to provide a refresh finished (RF) signal indicative that a refresh cycle is substantially completed; a burst refresh mode control circuit (134, 140) coupled to receive externally-applied signals and effective for determining whether the memory circuit should enter burst refresh mode; and a selectively operable burst refresh mode circuit (132) responsively coupled to said burst refresh mode control circuit, the burst refresh mode circuit being coupled to said control signal circuit (102) and coupled to receive said refresh finished signal (RF) from said detector circuit (126), said burst refresh mode circuit being effective to cause said memory circuit to generate successive addresses for refreshing rows of memory cells in response to successive ones of said refresh finished signal (RF).

Claim 26

The memory circuit of claim 20 wherein said burst refresh mode control circuit includes a burst refresh mode logic circuit (134) providing a counting function to determine when all rows of the memory circuit have been refreshed in the burst refresh mode.

Claim 27

The memory circuit of claim 20 further comprising a delay circuit coupled to receive a precharge clock signal produced by said precharge and clock circuit and to provide a delayed timing signal based thereon to said burst refresh mode circuit.