Method and apparatus for refreshing a dynamic random access memory

Claim 1

An apparatus for refreshing a DRAM having a plurality of rows of memory cells comprising: cycle initiating means for initiating one of a normal cycle or a refresh cycle; mode control means, coupled to the cycle initiating means, for generating a normal mode signal when the normal cycle is initiated and for generating a refresh mode signal when the refresh cycle is initiated; row address means, coupled to the mode control means, for addressing a first number of rows of memory cells in response to the normal mode signal and for addressing a second number of rows of memory cells in response to the refresh mode signal; wherein the first number of rows is less than the second number of rows; row strobe receiving means for receiving a row address strobe signal; column strobe receiving means for receiving a column address strobe signal; wherein the mode control means is coupled to the row strobe receiving means and to the column strobe receiving means for generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received and for generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; external address input means for receiving an external address; wherein the row address means is coupled to the external address input means for addressing the first number of rows of memory cells using the external address in response to the normal mode signal; wherein the mode control means generates an incrementing signal when the row address strobe signal is received not before the column address strobe signal is received; wherein the row address means further comprises a counter, coupled to the mode control means, for storing a counter value, the counter value being incremented in response to the incrementing signal; and wherein the second number of rows of data are addressed using the counter value as an address in response to the refresh mode signal.

Claim 2

An apparatus for refreshing a DRAM having a plurality of rows of memory cells comprising: cycle initiating means for initiating one of a normal cycle or a refresh cycle; mode control means, coupled to the cycle initiating means, for generating a normal mode signal when the normal cycle is initiated and for generating a refresh mode signal when the refresh cycle is initiated; row address means, coupled to the mode control means, for addressing a first number of rows of memory cells in response to the normal mode signal and for addressing a second number of rows of memory cells in response to the refresh mode signal; wherein the first number of rows is less than the second number of rows; row strobe receiving means for receiving a row address strobe signal; column strobe receiving means for receiving a column address strobe signal; wherein the mode control means is coupled to the row strobe receiving means and to the column strobe receiving means for generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received and for generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; external address input means for receiving an external address; wherein the row address means is coupled to the external address input means for addressing the first number of rows of memory cells using the external address in response to the normal mode signal; wherein the mode control means generates an incrementing signal when the row address strobe signal is received not before the column address strobe signal is received; wherein the row address means further comprises a counter, coupled to the mode control means, for storing a counter value, the counter value being incremented in response to the incrementing signal; and wherein the second number of rows of data are addressed using the counter value as an address in response to the refresh mode signal.

Claim 6

An apparatus for refreshing a DRAM having a plurality of arrays of memory cells, each array having a plurality of word lines and a plurality of memory cells coupled to each word line comprising: cycle initiating means for initiating one of a normal cycle or a refresh cycle; mode control means, coupled to the cycle initiating means, for generating a normal mode signal when the normal cycle is initiated and for generating a refresh mode signal when the refresh cycle is initiated; array address means, coupled to the mode control means, for providing an activating signal to a first number of word lines in response to the normal mode signal and for providing the activating signal to a second number of word lines in response to the refresh mode signal; wherein the first number of word lines is less than the second number of word lines; row strobe receiving means for receiving a row address strobe signal; column strobe receiving means for receiving a column address strobe signal; wherein the mode control means is coupled to the row strobe receiving means and to the column strobe receiving means for generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received and for generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; external address input means for receiving an eternal address; wherein the array address means is coupled to the external address input means for providing the activating signal to the first number of word lines using the external address in response to the normal mode signal; wherein the mode control means generates an incrementing signal when the row-address strobe signal is received not before the column address strobe signal is received; wherein the array address means further comprises a counter, coupled to the mode control means, for storing a counter value, the counter value being incremented in response to the incrementing signal; and wherein the array address means provides the activating signal to the second number of word lines using the counter value as an address in response to the refresh mode signal.

Claim 7

An apparatus for refreshing a DRAM having a plurality of arrays of memory cells, each array having a plurality of word lines and a plurality of memory cells coupled to each word line comprising: cycle initiating means for initiating one of a normal cycle or a refresh cycle; mode control means, coupled to the cycle initiating means, for generating a normal mode signal when the normal cycle is initiated and for generating a refresh mode signal when the refresh cycle is initiated; array address means, coupled to the mode control means, for providing an activating signal to a first number of word lines in response to the normal mode signal and for providing the activating signal to a second number of word lines in response to the refresh mode signal; wherein the first number of word lines is less than the second number of word lines; row strobe receiving means for receiving a row address strobe signal; column strobe receiving means for receiving a column address strobe signal; wherein the mode control means is coupled to the row strobe receiving means and to the column strobe receiving means for generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received and for generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; external address input means for receiving an eternal address; wherein the array address means is coupled to the external address input means for providing the activating signal to the first number of word lines using the external address in response to the normal mode signal; wherein the mode control means generates an incrementing signal when the row-address strobe signal is received not before the column address strobe signal is received; wherein the array address means further comprises a counter, coupled to the mode control means, for storing a counter value, the counter value being incremented in response to the incrementing signal; and wherein the array address means provides the activating signal to the second number of word lines using the counter value as an address in response to the refresh mode signal.

Claim 11

A method for refreshing a DRAM having a plurality of rows of memory cells comprising the steps of: initiating one of a normal cycle or a refresh cycle; generating a normal mode signal when a refresh cycle is initiated; addressing a first number of rows of data in response to the normal mode signal; addressing a second number of rows of data in response to the refresh mode signal; wherein the first number of rows is less than the second number of rows; receiving a row address strobe signal; receiving a column address strobe signal; wherein the normal mode signal generating step comprises the step of generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received; wherein the refresh mode signal generating step comprises the step of generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; receiving an external address; wherein the step of addressing the first number of rows of data comprises the step of addressing the first number of rows of data using the external address in response to the normal mode signal; storing a counter value; incrementing the counter value when the row address strobe signal is received not before the column address strobe signal is received; and wherein the step of addressing the second number of rows comprises the step of addressing the second number of rows of data using the counter value as an address in response to the refresh mode signal.

Claim 12

A method for refreshing a DRAM having a plurality of rows of memory cells comprising the steps of: initiating one of a normal cycle or a refresh cycle; generating a normal mode signal when a refresh cycle is initiated; addressing a first number of rows of data in response to the normal mode signal; addressing a second number of rows of data in response to the refresh mode signal; wherein the first number of rows is less than the second number of rows; receiving a row address strobe signal; receiving a column address strobe signal; wherein the normal mode signal generating step comprises the step of generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received; wherein the refresh mode signal generating step comprises the step of generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; receiving an external address; wherein the step of addressing the first number of rows of data comprises the step of addressing the first number of rows of data using the external address in response to the normal mode signal; storing a counter value; incrementing the counter value when the row address strobe signal is received not before the column address strobe signal is received; and wherein the step of addressing the second number of rows comprises the step of addressing the second number of rows of data using the counter value as an address in response to the refresh mode signal.

Claim 16

A method of refreshing a DRAM having a plurality of arrays of memory cells, each array having a plurality of word lines and a plurality of memory cells coupled to each word line comprising the steps of: initiating one of a normal cycle or a refresh cycle; generating a normal mode signal when a normal cycle is initiated; generating a refresh mode signal when a refresh cycle is initiated; providing an activating signal to a first number of word lines in response to the normal mode signal; providing an activating signal to a second number of word lines in response to the refresh mode signal; wherein the first number of word lines is less than the second number of word lines; receiving a row address strobe signal; receiving a column address strobe signal; wherein the step of generating the normal mode signal comprises the step of generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received; wherein the step of generating the refresh mode signal comprises the step of generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; receiving an external address; wherein the step of providing the activating signal to the first number of word lines comprises the step of providing the activating signal to the first number of word lines using the external address in response to the normal mode signal; storing a counter value; incrementing the counter value when the row address strobe is received not before the column address strobe signal is received; and wherein the step of providing the activating signal to the second number of word lines comprises the step of providing the activating signal to the second number of word lines using the counter value as an address in response to the refresh mode signal.

Claim 17

A method of refreshing a DRAM having a plurality of arrays of memory cells, each array having a plurality of word lines and a plurality of memory cells coupled to each word line comprising the steps of: initiating one of a normal cycle or a refresh cycle; generating a normal mode signal when a normal cycle is initiated; generating a refresh mode signal when a refresh cycle is initiated; providing an activating signal to a first number of word lines in response to the normal mode signal; providing an activating signal to a second number of word lines in response to the refresh mode signal; wherein the first number of word lines is less than the second number of word lines; receiving a row address strobe signal; receiving a column address strobe signal; wherein the step of generating the normal mode signal comprises the step of generating the normal mode signal when the row address strobe signal is received before the column address strobe signal is received; wherein the step of generating the refresh mode signal comprises the step of generating the refresh mode signal when the row address strobe signal is received not before the column address strobe signal is received; receiving an external address; wherein the step of providing the activating signal to the first number of word lines comprises the step of providing the activating signal to the first number of word lines using the external address in response to the normal mode signal; storing a counter value; incrementing the counter value when the row address strobe is received not before the column address strobe signal is received; and wherein the step of providing the activating signal to the second number of word lines comprises the step of providing the activating signal to the second number of word lines using the counter value as an address in response to the refresh mode signal.