Refreshing apparatus for MOS dynamic RAMs

Claim 2

A dynamic metal-oxide-semiconductor (MOS) random-access memory (RAM), comprising: a plurality of lines each coupled to at least one dynamic memory cell; decoding means coupled to said plurality of lines, for receiving externally generated address signals and for selecting one of said plurality of lines such that data may be read into and from at least said one memory cell coupled to said selected line, said decoding means for receiving said externally generated address signals during refreshing to identify cells for refreshing; refreshing means for refreshing data stored in said dynamic memory cells, said refreshing means coupled to said decoding means such that during refreshing at least two of said plurality of lines are selected by said decoding means for each of said externally generated address signals; whereby said dynamic memory cells may be more quickly refreshed.

Claim 3

The MOS RAM defined by claim 1 wherein said RAM is divided into at least two memory arrays.

Claim 4

The MOS RAM defined by claim 2 wherein each of said arrays includes a row of sensing amplifiers, said sensing amplifier being employed for refreshing.

Claim 5

The MOS RAM defined by claim 3 wherein one bit of said address signals is used for selecting one of said arrays such that said one of said plurality of lines in said arrays may be selected.

Claim 6

The MOS RAM defined by claim 4 wherein said refreshing means overides the effect of said one bit during refreshing.

Claim 7

The MOS RAM defined by claim 5 including refresh detection means for detecting a refresh condition and for generating a refresh signal, said refresh detection means coupled to said decoding means.

Claim 8

The MOS RAM defined by claim 6 wherein said refresh detection means is coupled to a source of address timing signals.

Claim 9

In a metal-oxide-semiconductor memory system which includes a plurality of dynamic storage arrays, each array including decoding means for decoding first externally generated address signals which are coupled to each of said arrays such that a line is selectable in each of said arrays and for receiving said externally generated first address signals during refreshing to identify a line in each of said arrays for refreshing; an apparatus for simultaneously refreshing memory cells in each of said arrays and for accessing a single line in one of said arrays comprising: identification means coupled to each of said arrays for receiving a second externally generated address signal and for identifying one of said arrays in response to said second address signal such that a single array line may be accessed in said one of said arrays by said first address signals; disabling means coupled to said identification means for disabling said identification means during refreshing such that said first externally generated address signals select an array line in each of said plurality of arrays; whereby a plurality of memory cells along said selected array lines may be simultaneously refreshed.

Claim 10

In a metal-oxide-semiconductor memory system which includes a plurality of dynamic storage arrays, each array including decoding means for decoding first externally generated address signals which are coupled to each of said arrays such that a line is selectable in each of said arrays and for receiving said externally generated first address signals during refreshing to identify a line in each of said arrays for refreshing; an apparatus for simultaneously refreshing memory cells in each of said arrays and for accessing a single line in one of said arrays comprising: identification means coupled to each of said arrays for receiving a second externally generated address signal and for identifying one of said arrays in response to said second address signal such that a single array line may be accessed in said one of said arrays by said first address signals; disabling means coupled to said identification means for disabling said identification means during refreshing such that said first externally generated address signals select an array line in each of said plurality of arrays; whereby a plurality of memory cells along said selected array lines may be simultaneously refreshed.

Claim 11

The apparatus defined by claim 8 wherein said disabling means includes detection means for detecting a refresh condition.