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US4079462A
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Refreshing apparatus for MOS dynamic RAMs
Assignee: Intel Corp
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Filing: 1976-05-07
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Granted: 1978-03-14
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Expires: 1996-05-07
Abstract
Abstract A refreshing apparatus for an MOS dynamic RAM which permits a 128 line × 128 line memory to be refreshed in 64 cycles. The row decoders operate with one less address bit during the refreshing cycle, thereby permitting the simultaneous selection of two row lines. The memory includes two rows of column amplifiers to facilitate the refreshing of cells coupled to two selected row lines.
Inventors
- 👤 James T. Koo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
136 words
A dynamic metal-oxide-semiconductor (MOS) random-access memory (RAM), comprising: a plurality of lines each coupled to at least one dynamic memory cell; decoding means coupled to said plurality of lines, for receiving externally generated address signals and for selecting one of said plurality of lines such that data may be read into and from at least said one memory cell coupled to said selected line, said decoding means for receiving said externally generated address signals during refreshing to identify cells for refreshing; refreshing means for refreshing data stored in said dynamic memory cells, said refreshing means coupled to said decoding means such that during refreshing at least two of said plurality of lines are selected by said decoding means for each of said externally generated address signals; whereby said dynamic memory cells may be more quickly refreshed.
Claim 2
Dependent Claim
136 words
A dynamic metal-oxide-semiconductor (MOS) random-access memory (RAM), comprising: a plurality of lines each coupled to at least one dynamic memory cell; decoding means coupled to said plurality of lines, for receiving externally generated address signals and for selecting one of said plurality of lines such that data may be read into and from at least said one memory cell coupled to said selected line, said decoding means for receiving said externally generated address signals during refreshing to identify cells for refreshing; refreshing means for refreshing data stored in said dynamic memory cells, said refreshing means coupled to said decoding means such that during refreshing at least two of said plurality of lines are selected by said decoding means for each of said externally generated address signals; whereby said dynamic memory cells may be more quickly refreshed.
Claim 3
Dependent Claim
18 words
The MOS RAM defined by claim 1 wherein said RAM is divided into at least two memory arrays.
Claim 4
Dependent Claim
25 words
The MOS RAM defined by claim 2 wherein each of said arrays includes a row of sensing amplifiers, said sensing amplifier being employed for refreshing.
Claim 5
Dependent Claim
37 words
The MOS RAM defined by claim 3 wherein one bit of said address signals is used for selecting one of said arrays such that said one of said plurality of lines in said arrays may be selected.
Claim 6
Dependent Claim
20 words
The MOS RAM defined by claim 4 wherein said refreshing means overides the effect of said one bit during refreshing.
Claim 7
Dependent Claim
31 words
The MOS RAM defined by claim 5 including refresh detection means for detecting a refresh condition and for generating a refresh signal, said refresh detection means coupled to said decoding means.
Claim 8
Dependent Claim
21 words
The MOS RAM defined by claim 6 wherein said refresh detection means is coupled to a source of address timing signals.
Claim 9
Dependent Claim
188 words
In a metal-oxide-semiconductor memory system which includes a plurality of dynamic storage arrays, each array including decoding means for decoding first externally generated address signals which are coupled to each of said arrays such that a line is selectable in each of said arrays and for receiving said externally generated first address signals during refreshing to identify a line in each of said arrays for refreshing; an apparatus for simultaneously refreshing memory cells in each of said arrays and for accessing a single line in one of said arrays comprising: identification means coupled to each of said arrays for receiving a second externally generated address signal and for identifying one of said arrays in response to said second address signal such that a single array line may be accessed in said one of said arrays by said first address signals; disabling means coupled to said identification means for disabling said identification means during refreshing such that said first externally generated address signals select an array line in each of said plurality of arrays; whereby a plurality of memory cells along said selected array lines may be simultaneously refreshed.
Claim 10
Dependent Claim
188 words
In a metal-oxide-semiconductor memory system which includes a plurality of dynamic storage arrays, each array including decoding means for decoding first externally generated address signals which are coupled to each of said arrays such that a line is selectable in each of said arrays and for receiving said externally generated first address signals during refreshing to identify a line in each of said arrays for refreshing; an apparatus for simultaneously refreshing memory cells in each of said arrays and for accessing a single line in one of said arrays comprising: identification means coupled to each of said arrays for receiving a second externally generated address signal and for identifying one of said arrays in response to said second address signal such that a single array line may be accessed in said one of said arrays by said first address signals; disabling means coupled to said identification means for disabling said identification means during refreshing such that said first externally generated address signals select an array line in each of said plurality of arrays; whereby a plurality of memory cells along said selected array lines may be simultaneously refreshed.
Claim 11
Dependent Claim
18 words
The apparatus defined by claim 8 wherein said disabling means includes detection means for detecting a refresh condition.
References Cited (Backward Citations)
US3760379A
Cited
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-13 | 1981-09-12 | 1982-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-13 | 1985-09-12 | 1986-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-13 | 1989-09-12 | 1990-03-14 | $7700.00 | Window Closed / Lapsed |