Processor system using on-chip refresh address generator for dynamic memory

Claim 2

A processing system comprising: (a) a semiconductor memory device comprising an array of rows and columns of memory cells in a single integrated circuit formed in a semiconductor body, the memory device having a refresh address counter included within said body for generating row addresses along with means for changing the address in the counter to produce a sequence for row addresses including all of the rows within a refresh period and having addressing means for alternatively receiving an address from inputs to the device or from the counter and for accessing the array using said address; and (b) processing means external to the integrated circuit for generating address signals and coupling them to the inputs of the integrated circuit.

Claim 3

A system according to claim 1 wherein the processing means generates said address signals to access data in said memory device.

Claim 6

A method according to claim 3 wherein said step of changing said refresh address includes the step of changing the contents of a counter within said integrated circuit; said counter being used in said step of generating row addresses.

Claim 7

A method according to claim 4 wherein said step of changing the contents is performed in response to control signals received from said processor device.

Claim 8

A method according to claim 5 wherein said control signals include a row-address strobe signal and another signal.

Claim 9

A method according to claim 6 wherein said step of selectively accessing said array is done with said data-access addresses or said refresh addresses in response to the conditions of said row-address strobe signal and said another signal.

Claim 10

A processing system comprising: (a) at least one semiconductor memory device, each memory device including an integrated circuit having: an array of rows and columns of memory cells of the type storing data using capacitor means and requiring periodic refresh of the data; a refresh address counter for producing a sequence of refresh addresses; addressing means for the array connected to receive an address either from terminals of the device or from said address counter; a first input to the device for an address-strobe signal; a second input to the device for another control signal; and control means for said addressing means responsive to at least said address-strobe signal and said another control signal to select between an address from said terminals or an address from said address counter for addressing said array; (b) processing means having a CPU and including means for applying addresses to said terminals and applying at least said first address strobe signal to said first input and for applying said another control signal to said second input.

Claim 11

A processing system comprising: (a) at least one semiconductor memory device, each memory device including an integrated circuit having: an array of rows and columns of memory cells of the type storing data using capacitor means and requiring periodic refresh of the data; a refresh address counter for producing a sequence of refresh addresses; addressing means for the array connected to receive an address either from terminals of the device or from said address counter; a first input to the device for an address-strobe signal; a second input to the device for another control signal; and control means for said addressing means responsive to at least said address-strobe signal and said another control signal to select between an address from said terminals or an address from said address counter for addressing said array; (b) processing means having a CPU and including means for applying addresses to said terminals and applying at least said first address strobe signal to said first input and for applying said another control signal to said second input.

Claim 12

A system according to claim 8 wherein said first address-strobe signal is a row address strobe.

Claim 13

A system according to claim 9 wherein said addressing means addresses said array using said address from terminals of said device if said another control signal is inactive when said address-strobe signal is active, or addresses said array using said address from said address counter if said another control signal is active when said address-strobe signal is active.

Claim 14

A system according to claim 10 wherein each of said address-strobe signal and said another control signal is active when at a zero voltage level and inactive when at a positive voltage level.