US6551885B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low temperature process for a thin film transistor
Assignee: GlobalFoundries US Inc
•
Filing: 2001-02-09
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Granted: 2003-04-22
•
Expires: 2021-02-09
Abstract
Abstract A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.
Inventors
- 👤 Bin Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/6737; H10D30/674; H10D30/6741; H10D30/6743; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
114 words
A method of manufacturing an integrated circuit, the integrated circuit including a thin film transistor on a substrate, the substrate including a thin semiconductor layer, the method comprising steps of: providing a sacrificial gate structure on the thin semiconductor layer of the substrate; etching the substrate in accordance with the sacrificial gate structure; providing an amorphous semiconductor layer above the substrate and over the gate structure; removing a portion of the amorphous semiconductor layer to expose the gate structure; forming a single crystalline semiconductor material from the amorphous semiconductor material; siliciding the single crystalline material; removing the sacrificial gate structure to form an aperture; and providing a high-k gate dielectric layer in the aperture.
Claim 2
Independent Claim
114 words
A method of manufacturing an integrated circuit, the integrated circuit including a thin film transistor on a substrate, the substrate including a thin semiconductor layer, the method comprising steps of: providing a sacrificial gate structure on the thin semiconductor layer of the substrate; etching the substrate in accordance with the sacrificial gate structure; providing an amorphous semiconductor layer above the substrate and over the gate structure; removing a portion of the amorphous semiconductor layer to expose the gate structure; forming a single crystalline semiconductor material from the amorphous semiconductor material; siliciding the single crystalline material; removing the sacrificial gate structure to form an aperture; and providing a high-k gate dielectric layer in the aperture.
Claim 3
Dependent Claim
14 words
The method of claim 1 , further comprising: providing a spacer in the aperture.
Claim 4
Dependent Claim
15 words
The method of claim 2 , further comprising: providing a gate conductor in the aperture.
Claim 5
Dependent Claim
15 words
The method of claim 3 , wherein the siliciding step is a cobalt silicide process.
Claim 6
Dependent Claim
14 words
The method of claim 1 , wherein the sacrificial gate structure includes silicon nitride.
Claim 7
Dependent Claim
16 words
The method of claim 1 , wherein the amorphous semiconductor layer is an in-situ doped layer.
Claim 8
Dependent Claim
13 words
The method of claim 6 , wherein the amorphous semiconductor material includes silicon.
Claim 9
Dependent Claim
13 words
The method of claim 1 , wherein the substrate includes single crystalline silicon.
Claim 10
Dependent Claim
14 words
The method of claim 1 , wherein the amorphous semiconductor layer includes silicon germanium.
Claim 11
Independent Claim
83 words
A method of manufacturing an ultra-large scale integrated circuit including a transistor, the method comprising: providing a mask structure on a top surface of a thin film; depositing a semiconductor material above the top surface of the thin film and the mask structure; removing the semiconductor material to a level below a top surface of the mask structure; siliciding the semiconductor material; removing the mask structure to leave an aperture; and providing a gate structure in the aperture including a high-k gate dielectric.
Claim 12
Independent Claim
83 words
A method of manufacturing an ultra-large scale integrated circuit including a transistor, the method comprising: providing a mask structure on a top surface of a thin film; depositing a semiconductor material above the top surface of the thin film and the mask structure; removing the semiconductor material to a level below a top surface of the mask structure; siliciding the semiconductor material; removing the mask structure to leave an aperture; and providing a gate structure in the aperture including a high-k gate dielectric.
Claim 13
Dependent Claim
23 words
The method of claim 10 , further comprising: providing an insulative layer over the silicided semiconductor material before the gate structure is provided.
Claim 14
Dependent Claim
21 words
The method of claim 11 , further comprising: providing a source and drain dopant implant before the insulative layer is provided.
Claim 15
Dependent Claim
15 words
The method of claim 12 , wherein the high-k gate dielectric is a metal oxide.
Claim 16
Dependent Claim
19 words
The method of claim 13 , wherein the siliciding is performed at a temperature of more than 800° C.
Claim 17
Dependent Claim
23 words
The method of claim 11 , wherein the insulative layer has a top surface co-planer with a top surface of the mask structure.
Claim 18
Dependent Claim
16 words
The method of claim 10 , wherein the mask structure is a sacrificial nitride gate structure.
Claim 19
Independent Claim
173 words
A method of fabricating a transistor on a thin film; the transistor including a gate structure having a high-k gate dielectric above the thin film and a gate conductor above a portion of the high-k gate dielectric, a source region and a drain region, the source and drain regions being adjacent the gate structure, the transistor including a silicide layer having a top surface above a bottom surface of the gate conductor and below a top surface of the gate conductor, the high gate dielectric being at least partially above the top surface of the silicide layer, the method comprises: providing a mask structure on the top surface of the thin film; depositing a semiconductor material above the top surface of the thin film and the mask structure; removing the semiconductor material to a level below a top surface of the mask structure; siliciding the semiconductor material to form the suicide layer; removing the mask structure to leave an aperture; and providing the gate structure in the aperture including the high-k gate dielectric.
Claim 20
Independent Claim
173 words
A method of fabricating a transistor on a thin film; the transistor including a gate structure having a high-k gate dielectric above the thin film and a gate conductor above a portion of the high-k gate dielectric, a source region and a drain region, the source and drain regions being adjacent the gate structure, the transistor including a silicide layer having a top surface above a bottom surface of the gate conductor and below a top surface of the gate conductor, the high gate dielectric being at least partially above the top surface of the silicide layer, the method comprises: providing a mask structure on the top surface of the thin film; depositing a semiconductor material above the top surface of the thin film and the mask structure; removing the semiconductor material to a level below a top surface of the mask structure; siliciding the semiconductor material to form the suicide layer; removing the mask structure to leave an aperture; and providing the gate structure in the aperture including the high-k gate dielectric.
Claim 21
Dependent Claim
21 words
The method of claim 17 , further comprising: providing a thin insulative layer between the silicide layer and the high-k dielectric.
Claim 22
Dependent Claim
12 words
The method of claim 17 , wherein the gate structure includes spacers.
Claim 23
Dependent Claim
23 words
The method of claim 19 , wherein the spacers are disposed between a portion of the high-k gate dielectric and the silicide layer.
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