US5654570A
Expired / Lapsed
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CMOS gate stack
Assignee: International Business Machines Corp
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Filing: 1995-04-19
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Granted: 1997-08-05
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Expires: 2015-04-19
Abstract
Abstract A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain junction, and is preferably of greater width than the gate.
Inventors
- 👤 Paul David Agnello
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:01
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
66 words
A CMOS gate stack comprising a semiconductor substrate; device isolation regions on or in said substrate or both on and in said substrate; gate isolation layer over active regions of said substrate as defined by said device isolation regions; polysilicon gate located above said gate isolation layer; self-aligned metallic gate conductor above said polysilicon gate wherein said metallic gate conductor is wider than said polysilicon gate.
Claim 2
Dependent Claim
66 words
A CMOS gate stack comprising a semiconductor substrate; device isolation regions on or in said substrate or both on and in said substrate; gate isolation layer over active regions of said substrate as defined by said device isolation regions; polysilicon gate located above said gate isolation layer; self-aligned metallic gate conductor above said polysilicon gate wherein said metallic gate conductor is wider than said polysilicon gate.
Claim 3
Dependent Claim
11 words
The gate stack of claim 1 wherein said substrate is silicon.
Claim 4
Dependent Claim
14 words
The gate stack of claim 1 wherein said device isolation regions is silicon dioxide.
Claim 5
Dependent Claim
12 words
The gate stack of claim 1 which further comprises a cap dielectric.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |