US6087235A
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Method for effective fabrication of a field effect transistor with elevated drain and source contact structures
Assignee: GlobalFoundries Inc
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Filing: 1999-10-14
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Granted: 2000-07-11
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Expires: 2019-10-14
Abstract
Abstract A field effect transistor is fabricated to have elevated drain and source contact structures with prevention of short-channel effects and leakage current which may result due to the formation of facetted surfaces on the elevated drain and source contact structures near the gate of the field effect transistor. The field effect transistor includes a drain extension implant, a source extension implant, a gate dielectric, a gate structure disposed over the gate dielectric, and a first spacer disposed on sidewalls of the gate dielectric and of the gate structure. An elevated drain contact structure is selectively grown on the drain extension implant and has a drain facetted surface facing toward the first spacer on the sidewall of the gate structure. Similarly, an elevated source contact structure is selectively grown on the source extension implant and has a source facetted surface facing toward the first spacer on the sidewall of the gate structure. A second spacer is formed to cover the drain facetted surface and the source facetted surface before dopant implantation into and silicide formation on the elevated drain and source contact structures. In this manner, the dopant is prevented from being implanted into the drain facetted surface and the source facetted surface such that short-channel effects are minimized in the field effect transistor of the present invention. In addition, formation of silicide on the drain facetted surface and the source facetted surface is prevented to minimize leakage current through the drain and source extension implants of the field effect transistor of the present invention.
Inventors
- 👤 Bin Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:05
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/027; H10D30/0275; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
277 words
A method for fabricating a field effect transistor having a drain extension implant, a source extension implant, a gate dielectric, a gate structure disposed over said gate dielectric, and a first spacer disposed on sidewalls of said gate dielectric and of said gate structure, the method including the steps of: A. selectively growing an elevated drain contact structure on said drain extension implant, said elevated drain contact structure having a drain facetted surface facing toward said first spacer on said sidewall of said gate structure; B. selectively growing an elevated source contact structure on said source extension implant, said elevated source contact structure having a source facetted surface facing toward said first spacer on said sidewall of said gate structure; C. forming a second spacer to cover said drain facetted surface and said source facetted surface; D. doping said elevated drain contact structure and said elevated source contact structure that is exposed with a dopant, after said step C; E. activating said dopant within said elevated drain contact structure and said elevated source contact structure; F. forming silicide on said elevated drain contact structure and said elevated source contact structure that is exposed, after said step E; forming a gate capping layer on said gate structure before said step A to prevent selective growth of said gate structure into a mushroom-shaped structure during said step A; etching said gate capping layer on said gate structure, after said step C and before said step D; doping said gate structure with said dopant during said step D; activating said dopant within said gate structure during said step E; and forming silicide on said gate structure during said step F.
Claim 2
Independent Claim
277 words
A method for fabricating a field effect transistor having a drain extension implant, a source extension implant, a gate dielectric, a gate structure disposed over said gate dielectric, and a first spacer disposed on sidewalls of said gate dielectric and of said gate structure, the method including the steps of: A. selectively growing an elevated drain contact structure on said drain extension implant, said elevated drain contact structure having a drain facetted surface facing toward said first spacer on said sidewall of said gate structure; B. selectively growing an elevated source contact structure on said source extension implant, said elevated source contact structure having a source facetted surface facing toward said first spacer on said sidewall of said gate structure; C. forming a second spacer to cover said drain facetted surface and said source facetted surface; D. doping said elevated drain contact structure and said elevated source contact structure that is exposed with a dopant, after said step C; E. activating said dopant within said elevated drain contact structure and said elevated source contact structure; F. forming silicide on said elevated drain contact structure and said elevated source contact structure that is exposed, after said step E; forming a gate capping layer on said gate structure before said step A to prevent selective growth of said gate structure into a mushroom-shaped structure during said step A; etching said gate capping layer on said gate structure, after said step C and before said step D; doping said gate structure with said dopant during said step D; activating said dopant within said gate structure during said step E; and forming silicide on said gate structure during said step F.
Claim 3
Dependent Claim
38 words
The method of claim 1, wherein said second spacer covers said first spacer disposed on said sidewalls of said gate structure such that said first spacer is not etched during said step of etching said gate capping layer.
Claim 4
Dependent Claim
39 words
The method of claim 2, wherein said first spacer is comprised of silicon nitride (SiN), wherein said gate capping layer is comprised of silicon nitride (SiN), and wherein said second spacer is comprised of silicon dioxide (SiO 2 ).
Claim 5
Dependent Claim
53 words
The method of claim 3, wherein said gate structure is comprised of polysilicon, and wherein said elevated drain contact structure is formed by selective epitaxial growth of silicon on said drain extension implant, and wherein said elevated source contact structure is formed by selective epitaxial growth of silicon on said source extension implant.
Claim 6
Dependent Claim
19 words
The method of claim 1, wherein said field effect transistor is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
Claim 7
Dependent Claim
23 words
The method of claim 5, wherein said dopant is an N-type dopant for fabricating an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor).
Claim 8
Dependent Claim
23 words
The method of claim 5, wherein said dopant is a P-type dopant for fabricating a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).
Claim 9
Independent Claim
355 words
A method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain extension implant, a source extension implant, a gate oxide, a polysilicon gate disposed over said gate oxide, and a first spacer comprised of silicon nitride disposed on sidewalls of said gate oxide and of said polysilicon gate, the method including the steps of: A. forming a gate capping layer on said polysilicon gate; B. growing an elevated drain contact structure by selective epitaxial growth of silicon on said drain extension implant, said elevated drain contact structure having a drain facetted surface facing toward said first spacer on said sidewall of said polysilicon gate; C. growing an elevated source contact structure by selective epitaxial growth of silicon on said source extension implant, said elevated source contact structure having a source facetted surface facing toward said first spacer on said sidewall of said polysilicon gate; wherein said gate capping layer prevents selective epitaxial growth of silicon on said polysilicon gate during said step B and said step C; D. forming a second spacer of silicon dioxide to cover said drain facetted surface and said source facetted surface and to cover said first spacer comprised of silicon nitride on said sidewalls of said gate oxide and of said polysilicon gate; E. etching said gate capping layer on said polysilicon gate after said step D, wherein said second spacer covers said first spacer such that said first spacer is not etched during said step of etching said gate capping layer; F. doping said elevated drain contact structure and said elevated source contact structure that is exposed, and doping said polysilicon gate, with a dopant, said dopant being one of an N-type dopant for fabrication of an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) and of a P-type dopant for fabrication of a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor); G. activating said dopant within said elevated drain contact structure, said elevated source contact structure, and said polysilicon gate; and H. forming silicide on said elevated drain contact structure and said elevated source contact structure that is exposed, and on said polysilicon gate.
Claim 10
Independent Claim
355 words
A method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain extension implant, a source extension implant, a gate oxide, a polysilicon gate disposed over said gate oxide, and a first spacer comprised of silicon nitride disposed on sidewalls of said gate oxide and of said polysilicon gate, the method including the steps of: A. forming a gate capping layer on said polysilicon gate; B. growing an elevated drain contact structure by selective epitaxial growth of silicon on said drain extension implant, said elevated drain contact structure having a drain facetted surface facing toward said first spacer on said sidewall of said polysilicon gate; C. growing an elevated source contact structure by selective epitaxial growth of silicon on said source extension implant, said elevated source contact structure having a source facetted surface facing toward said first spacer on said sidewall of said polysilicon gate; wherein said gate capping layer prevents selective epitaxial growth of silicon on said polysilicon gate during said step B and said step C; D. forming a second spacer of silicon dioxide to cover said drain facetted surface and said source facetted surface and to cover said first spacer comprised of silicon nitride on said sidewalls of said gate oxide and of said polysilicon gate; E. etching said gate capping layer on said polysilicon gate after said step D, wherein said second spacer covers said first spacer such that said first spacer is not etched during said step of etching said gate capping layer; F. doping said elevated drain contact structure and said elevated source contact structure that is exposed, and doping said polysilicon gate, with a dopant, said dopant being one of an N-type dopant for fabrication of an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) and of a P-type dopant for fabrication of a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor); G. activating said dopant within said elevated drain contact structure, said elevated source contact structure, and said polysilicon gate; and H. forming silicide on said elevated drain contact structure and said elevated source contact structure that is exposed, and on said polysilicon gate.
References Cited (Backward Citations)
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