US6017808A
Expired / Lapsed
US
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Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening
Assignee: Bell Semiconductor LLC
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Filing: 1997-10-24
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Granted: 2000-01-25
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Expires: 2017-10-24
Abstract
Abstract A method for hardening of gate oxide without forming low dopant concentration regions at the gate oxide-polysilicon interface is described. Polysilicon is deposited onto gate oxide followed by nitrogen implantation and annealing. At this point nitrogen concentration peaks exist at the gate oxide interfaces with the single crystal substrate and the polysilicon gate electrode. This effectively hardens the gate oxide. A third polysilicon gate electrode exists in the bulk of the polysilicon gate electrode. In the described process the region of the polysilicon layer that contains the nitrogen concentration peak is removed. An electronically active dopant may then be implanted. Alternatively, a fresh polysilicon layer may then be deposited followed by implantation of an electronically active dopant. Thus, the method of the invention avoids retardation of electronically active dopant diffusion.
Inventors
- 👤 Shiuh-Luen Wang
- 👤 Chiang-Sheng Yao
- 👤 Wen-Chin Yeh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:01
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01344; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01326; H10D64/01338; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/68; H10D64/693
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
82 words
A method for hardening gate oxide in a partially fabricated electronic device, the method comprising: implanting nitrogen ions in a first polysilicon layer deposited on a gate oxide; annealing so that nitrogen concentrates on said gate oxide and a location in the bulk of said first polysilicon layer; and removing polysilicon from the top of said first polysilicon layer to provide a second polysilicon layer which does not include said location in the bulk of said first polysilicon layer where nitrogen concentrates.
Claim 2
Independent Claim
82 words
A method for hardening gate oxide in a partially fabricated electronic device, the method comprising: implanting nitrogen ions in a first polysilicon layer deposited on a gate oxide; annealing so that nitrogen concentrates on said gate oxide and a location in the bulk of said first polysilicon layer; and removing polysilicon from the top of said first polysilicon layer to provide a second polysilicon layer which does not include said location in the bulk of said first polysilicon layer where nitrogen concentrates.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein said gate oxide is less than about 50 Å thick.
Claim 4
Dependent Claim
20 words
The method of claim 1 further comprising the step of implanting an electronically active dopant in said second polysilicon layer.
Claim 5
Dependent Claim
12 words
The method of claim 3 wherein said electronically active dopant is boron.
Claim 6
Dependent Claim
12 words
The method of claim 3 wherein said electronically active dopant is phosphorus.
Claim 7
Dependent Claim
20 words
The method of claim 1 wherein said first polysilicon layer is between about 2000 Å and about 4000 Å thick.
Claim 8
Dependent Claim
20 words
The method of claim 6 wherein said second polysilicon layer is between about 750 Å and about 2500 Å thick.
Claim 9
Dependent Claim
18 words
The method of claim 1 wherein said annealing is performed between about 800° C. and about 1000° C.
Claim 10
Dependent Claim
14 words
The method of claim 8 wherein said annealing is performed at about 900° C.
Claim 11
Dependent Claim
17 words
The method of claim 1 wherein said partially fabricated electronic device is a partially fabricated NMOS device.
Claim 12
Dependent Claim
17 words
The method of claim 1 wherein said partially fabricated electronic device is a partially fabricated PMOS device.
Claim 13
Dependent Claim
23 words
The method of claim 1 further comprising depositing a third polysilicon layer onto said second polysilicon layer to provide a composite polysilicon layer.
Claim 14
Dependent Claim
15 words
The method claim 12 wherein said gate oxide is less than about 50 Å thick.
Claim 15
Dependent Claim
20 words
The method of claim 12 further comprising the step of implanting an electronically active dopant in said composite polysilicon layer.
Claim 16
Dependent Claim
12 words
The method of claim 14 wherein said electronically active dopant is boron.
Claim 17
Dependent Claim
20 words
The method of claim 12 wherein said first polysilicon layer is between about 2000 Å and about 4000 Å thick.
Claim 18
Dependent Claim
20 words
The method of claim 12 wherein said second polysilicon layer is between about 750 Å and about 2500 Å thick.
Claim 19
Dependent Claim
20 words
The method of claim 12 wherein said third polysilicon layer is between about 1000 Å and about 2000 Å thick.
Claim 20
Dependent Claim
20 words
The method of claim 12 wherein said composite polysilicon layer is between about 1500 Å and about 3500 Å thick.
Claim 21
Dependent Claim
17 words
The method of claim 12 wherein said partially fabricated electronic device is a partially fabricated PMOS device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-24 | 2003-07-26 | 2004-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-24 | 2007-07-26 | 2008-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-24 | 2011-07-26 | 2012-01-25 | $7700.00 | Window Closed / Lapsed |