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US5882974A Expired / Lapsed US ⏱️ 0.0 years remaining

High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel

Assignee: GlobalFoundries Inc
•
Filing: 1998-04-08
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Granted: 1999-03-16
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Expires: 2018-04-08
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Abstract

Abstract The present invention advantageously provides a method for forming a transistor having decreased source-side parasitic resistance and an improved shallow junction, thereby providing for enhanced transistor performance and improved resistance to short-channel effects. Barrier atoms are selectively implanted into the semiconductor substrate prior to formation of lightly doped drains and source/drain regions. Barrier atoms present in the channel region under the gate structure prevent migration of the lightly doped drain implant impurities into the channel region, thus reducing parasitic resistance. Barrier atoms implanted into the junction region prevent migration of source implant impurities more deeply into the junction region, thus preserving the shallow junction.

Inventors

  • 👤 Mark I. Gardner
  • 👤 H. Jim Fulford, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:09
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10P30/208; H10P30/225; H10P30/22

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 76 words
A method for forming a transistor comprising: providing a gate conductor dielectrically spaced over a channel area between a source region and a drain region; implanting a plurality of barrier atoms substantially through only a portion of the gate conductor exclusively into the channel area immediately adjacent the source region while concurrently implanting the plurality of barrier atoms into the source region; and implanting a plurality of dopant atoms into the source region and drain region.
Claim 2
Independent Claim 76 words
A method for forming a transistor comprising: providing a gate conductor dielectrically spaced over a channel area between a source region and a drain region; implanting a plurality of barrier atoms substantially through only a portion of the gate conductor exclusively into the channel area immediately adjacent the source region while concurrently implanting the plurality of barrier atoms into the source region; and implanting a plurality of dopant atoms into the source region and drain region.
Claim 3
Dependent Claim 52 words
The method of claim 1, wherein implanting barrier atoms comprises: patterning a masking layer to leave the source region exposed and only said portion of the gate conductor immediately adjacent the source region exposed; and introducing the plurality of barrier atoms into the exposed source region and the partially exposed gate conductor.
Claim 4
Dependent Claim 27 words
The method of claim 2, wherein said introducing comprises injecting the plurality of barrier atoms to a greater depth within said source region than said channel area.
Claim 5
Dependent Claim 53 words
The method of claim 2, wherein patterning the masking layer comprises: depositing a masking material across the entirety of said source region, said drain region and said gate conductor; and removing the masking material from said source region and from said gate conductor parallel to an axis along which the gate conductor extends.
Claim 6
Dependent Claim 34 words
The method of claim 2, wherein said introducing comprises injecting the plurality of barrier atoms to a peak concentration density within the source region deeper than a peak concentration density within the channel area.
Claim 7
Dependent Claim 27 words
The method of claim 2, wherein implanting the plurality of barrier atoms comprises implanting atomic species that are chemically and electrically inert to electrical stimuli placed thereon.
Claim 8
Dependent Claim 17 words
The method of claim 1, wherein implanting the plurality of dopant atoms comprises implanting boron atomic species.
Claim 9
Dependent Claim 19 words
The method of claim 1, wherein implanting the plurality of barrier atoms comprises implanting chemical species that contain nitrogen.
Claim 10
Dependent Claim 26 words
The method of claim 1, wherein implanting the plurality of dopant atoms comprises implanting a material selected from the group consisting of boron and boron difluoride.
Claim 11
Dependent Claim 31 words
The method of claim 1, wherein implanting the plurality of barrier atoms comprises implanting chemical species selected from the group consisting of N, N 2 , NO, and N 2 O.
Claim 12
Dependent Claim 58 words
The method of claim 1, wherein implanting the plurality of dopant atoms comprises: implanting p-type atomic species into the source and drain regions; forming a pair of spacers adjacent opposed sidewall surfaces of the gate conductor; and implanting p-type atomic species into the source and drain regions laterally spaced from the channel area by the pair of spacers.
Claim 13
Dependent Claim 40 words
The method of claim 11, wherein forming the pair of spacers comprises chemical-vapor depositing a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; and anisotropically removing the material except from the opposed sidewall surfaces.

References Cited (Backward Citations)

US4523213A Cited
US4700454A Cited
US4683637A Cited
US5567629A Cited
US5712173A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-03-15 2002-09-14 2003-03-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-03-15 2006-09-14 2007-03-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-03-15 2010-09-14 2011-03-16 $7700.00 Window Closed / Lapsed

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