Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing

Claim 2

A process for forming a semiconductor device, comprising: providing a single crystal semiconductor substrate having a first surface; forming on said surface a conductor means having a first predetermined thickness and overlying a first region of said substrate and not overlying a second region of said substrate; implanting oxygen or nitrogen into a first part of said second region of said substrate and into said conductor means to a dose exceeding about 1×10 18 ions/cm 2 at an energy sufficient to penetrate into said substrate to a first predetermined depth and to penetrate into said conductor means to a second predetermined depth less than said first thickness; heating said substrate and said conductor means to react said implanted oxygen or nitrogen to form a first buried dielectric at said first depth in said second region and a second buried dielectric at said second depth in said conductor means; etching away a first part of said conductor means above said second buried dielectric to leave said second dielectric and a second part of said conductor means below said second dielectric; and thereafter etching away said second buried dielectric.

Claim 3

The process of claim 1 further comprising after said steps of implanting oxygen or nitrogen and heating to form said first and second buried dielectrics, doping a part of said second region of said substrate with a conductivity altering dopant.

Claim 4

The process of claim 1 wherein said heating step comprises heating to a temperature exceeding about 1000° C.

Claim 5

The process of claim 1 further comprising forming a dielectric region on said surface under said conductor means.

Claim 6

The process of claim 2 further comprising prior to said doping step, forming dielectric isolation walls in another part of said second region of said substrate and extending from said surface to said first buried dielectric in said substrate.

Claim 7

A process for forming a partially isolated MOS transistor having source, drain and gate regions, comprising: providing a single crystal semiconductor substrate having a principle surface; forming an oxidation resistant masking layer on said surface; patterning said masking layer to expose first portions of said substrate; removing said first portions on said substrate to form trenches; at least partly refilling said trenches with dielectric to form isolation walls having a first depth; forming above said surface and said refilled trenches a conductor layer having a first thickness exceeding a second depth, wherein said second depth is a predetermined oxygen or nitrogen implant penetration depth in said conductor layer; removing a first portion of said conductor layer leaving behind a second portion of said conductor layer located between two of said isolation walls; implanting oxygen or nitrogen into said substrate and said conductor layer at an energy sufficient to penetrate to a third depth in said substrate and to said second depth in said conductor layer, wherein said third depth is less than or equal said first depth, and to a dose sufficient to form dielectric regions by reaction with said substrate and said conductor layer; heating to react said oxygen or nitrogen with said substrate and said conductor layer to form a first buried dielectric region lying at said second depth in said second portion of said conductor layer and a second buried dielectric region lying at said third depth in said substrate; and etching away said conductor layer above said first buried dielectric region and said first buried dielectric region.

Claim 8

A process for forming a partially isolated MOS transistor having source, drain and gate regions, comprising: providing a single crystal semiconductor substrate having a principle surface; forming an oxidation resistant masking layer on said surface; patterning said masking layer to expose first portions of said substrate; removing said first portions on said substrate to form trenches; at least partly refilling said trenches with dielectric to form isolation walls having a first depth; forming above said surface and said refilled trenches a conductor layer having a first thickness exceeding a second depth, wherein said second depth is a predetermined oxygen or nitrogen implant penetration depth in said conductor layer; removing a first portion of said conductor layer leaving behind a second portion of said conductor layer located between two of said isolation walls; implanting oxygen or nitrogen into said substrate and said conductor layer at an energy sufficient to penetrate to a third depth in said substrate and to said second depth in said conductor layer, wherein said third depth is less than or equal said first depth, and to a dose sufficient to form dielectric regions by reaction with said substrate and said conductor layer; heating to react said oxygen or nitrogen with said substrate and said conductor layer to form a first buried dielectric region lying at said second depth in said second portion of said conductor layer and a second buried dielectric region lying at said third depth in said substrate; and etching away said conductor layer above said first buried dielectric region and said first buried dielectric region.

Claim 9

The process of claim 6 further comprising, after said step of implanting oxygen or nitrogen, implanting a conductivity altering dopant into said second portion of said conductor layer and into part of said substrate.