US6008111A
Expired / Lapsed
US
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Method of manufacturing semiconductor device
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1997-03-13
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Granted: 1999-12-28
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Expires: 2017-03-13
Abstract
Abstract A manufacturing method of a semiconductor device of the present invention comprises the steps of forming an amorphous layer on an upper layer of the impurity diffusion layer made of silicon by virtue of ion-implantation, forming a cobalt film on the impurity diffusion layer, forming a cobalt silicide layer made of Co 2 Si or CoSi on an upper layer of the amorphous layer at a low temperature by reacting the cobalt film to silicon in the impurity diffusion layer in virtue of first annealing, then removing the cobalt film which has not reacted, and changing Co 2 Si or CoSi constituting the cobalt silicide layer into CoSi 2 to have low resistance and also rendering the cobalt silicide layer to enter into a depth identical to or deeper than an initial depth of the amorphous layer in virtue of second annealing.
Inventors
- 👤 Atsuo Fushida
- 👤 Kenichi Goto
- 👤 Tatsuya Yamazaki
- 👤 Takae Sukegawa
- 👤 Masataka Kase
- 👤 Takashi Sakuma
- 👤 Keisuke Okazaki
- 👤 Yuzuru Ota
- 👤 Hideo Takagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10P; H10P10/00; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
140 words
A method of manufacturing a semiconductor device, comprising the steps of: introducing impurities into an upper surface region of a silicon layer and then annealing, to thereby form an impurity diffusion layer; ion-implanting an element into the upper surface region of said silicon layer, to thereby form an amorphous layer; forming a cobalt film on said amorphous layer; annealing said cobalt film and said amorphous layer at a first temperature, to thereby form a cobalt silicide layer made of Co 2 Si or CoSi in an upper surface region of said amorphous layer; and annealing said cobalt silicide layer and said silicon layer at a second temperature, to thereby change said Co 2 Si or CoSi into CoSi 2 and also to make a depth of said cobalt silicide layer equal to or deeper than that of said amorphous layer.
Claim 2
Independent Claim
140 words
A method of manufacturing a semiconductor device, comprising the steps of: introducing impurities into an upper surface region of a silicon layer and then annealing, to thereby form an impurity diffusion layer; ion-implanting an element into the upper surface region of said silicon layer, to thereby form an amorphous layer; forming a cobalt film on said amorphous layer; annealing said cobalt film and said amorphous layer at a first temperature, to thereby form a cobalt silicide layer made of Co 2 Si or CoSi in an upper surface region of said amorphous layer; and annealing said cobalt silicide layer and said silicon layer at a second temperature, to thereby change said Co 2 Si or CoSi into CoSi 2 and also to make a depth of said cobalt silicide layer equal to or deeper than that of said amorphous layer.
Claim 3
Dependent Claim
14 words
The method according to claim 1, wherein said first temperature is below 450° C.
Claim 4
Dependent Claim
32 words
The method according to claim 1, wherein said second temperature is above 500° C. and is below a temperature at which the annealing to form said impurity diffusion layer is carried out.
Claim 5
Dependent Claim
21 words
The method according to claim 1, wherein said cobalt film is formed to have a thickness of 8 to 20 nm.
Claim 6
Dependent Claim
33 words
The method according to claim 1, further comprising, between said forming of the cobalt film and said annealing at the first temperature, a step of forming a cap layer on said cobalt film.
Claim 7
Dependent Claim
15 words
The method according to claim 5, wherein said cap layer is made of titanium nitride.
Claim 8
Dependent Claim
21 words
The method according to claim 1, wherein said element is one selected from the group consisting of germanium, silicon, and arsenic.
Claim 9
Dependent Claim
59 words
The method according to claim 7, wherein said germanium is ion-implanted with a dosage of more than 8×10 13 atoms/cm 2 , said silicon is ion-implanted with a dosage of more than 8×10 14 atoms/cm 2 , and said arsenic is ion-implanted with a dosage within a range of 8×10 13 atoms/cm 2 to 5×10 14 atoms/cm 2 .
Claim 10
Dependent Claim
37 words
The method according to claim 1, further comprising, between said annealing at the first temperature and said annealing at the second temperature, a step of removing said cobalt film which has not reacted with said amorphous layer.
Claim 11
Independent Claim
171 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode via a gate insulating layer on a silicon layer; introducing impurities into said silicon layer of both sides of said gate electrode and then annealing, to thereby form an impurity diffusion layer as a source/drain region; ion-implanting an element into an upper surface region of said silicon layer, to thereby form an amorphous layer; forming a cobalt film on said amorphous layer; annealing said cobalt film and said amorphous layer at a first temperature, to thereby form a cobalt silicide layer made of Co 2 Si or CoSi in an upper surface region of said amorphous layer; removing said cobalt film which has not reacted with said amorphous layer; and annealing said cobalt silicide layer and said silicon layer at a second temperature, to thereby change said Co 2 Si or CoSi into CoSi 2 and also to make a depth of said cobalt silicide layer equal to or deeper than that of said amorphous layer.
Claim 12
Independent Claim
171 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode via a gate insulating layer on a silicon layer; introducing impurities into said silicon layer of both sides of said gate electrode and then annealing, to thereby form an impurity diffusion layer as a source/drain region; ion-implanting an element into an upper surface region of said silicon layer, to thereby form an amorphous layer; forming a cobalt film on said amorphous layer; annealing said cobalt film and said amorphous layer at a first temperature, to thereby form a cobalt silicide layer made of Co 2 Si or CoSi in an upper surface region of said amorphous layer; removing said cobalt film which has not reacted with said amorphous layer; and annealing said cobalt silicide layer and said silicon layer at a second temperature, to thereby change said Co 2 Si or CoSi into CoSi 2 and also to make a depth of said cobalt silicide layer equal to or deeper than that of said amorphous layer.
Claim 13
Dependent Claim
40 words
The method according to claim 10, wherein said gate electrode is made of polysilicon; an upper surface region of the gate electrode is made amorphous by ion-implanting said element thereinto; and said cobalt film is formed on the gate electrode.
Claim 14
Dependent Claim
14 words
The method according to claim 10, wherein said first temperature is below 450° C.
Claim 15
Dependent Claim
32 words
The method according to claim 10, wherein said second temperature is above 500° C. and is below a temperature at which the annealing to form said impurity diffusion layer is carried out.
Claim 16
Dependent Claim
21 words
The method according to claim 10, wherein said cobalt film is formed to have a thickness of 8 to 20 nm.
Claim 17
Dependent Claim
33 words
The method according to claim 10, further comprising, between said forming of a cobalt film and said annealing at the first temperature, a step of forming a cap layer on said cobalt film.
Claim 18
Dependent Claim
15 words
The method according to claim 15, wherein said cap layer is made of titanium nitride.
Claim 19
Dependent Claim
20 words
The method according to claim 10, wherein said element is one selected from the group of germanium, silicon, and arsenic.
Claim 20
Dependent Claim
59 words
The method according to claim 17, wherein said germanium is ion-implanted with a dosage of more than 8×10 13 atoms/cm 2 , said silicon is ion-implanted with a dosage of more than 8×10 14 atoms/cm 2 , and said arsenic is ion-implanted with a dosage within a range of 8×10 13 atoms/cm 2 to 5×10 14 atoms/cm 2 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |