US6057200A
Expired / Lapsed
US
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Method of making a field effect transistor having an elevated source and an elevated drain
Assignee: Mosaid Technologies Inc
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Filing: 1997-04-01
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Granted: 2000-05-02
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Expires: 2017-04-01
Abstract
Abstract A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.
Inventors
- 👤 Kirk Prall
- 👤 Pai-Hung Pan
- 👤 Sujit Sharan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:27
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S438/00; Y10S438/969
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
67 words
A method of forming an elevated source/drain region comprising chemical vapor depositing a monocrystalline doped silicon layer over a substrate surface, the chemical vapor depositing comprising varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from proximate the substrate to outwardly therefrom.
Claim 2
Independent Claim
67 words
A method of forming an elevated source/drain region comprising chemical vapor depositing a monocrystalline doped silicon layer over a substrate surface, the chemical vapor depositing comprising varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from proximate the substrate to outwardly therefrom.
Claim 3
Independent Claim
120 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising: providing outer exposed surfaces of the monocrystalline silicon substrate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; after the cleaning, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and after the chemical vapor depositing, transforming at least a portion of the non-polycrystalline silicon to a polycrystalline silicon mass which is spaced from the substrate surface.
Claim 4
Independent Claim
120 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising: providing outer exposed surfaces of the monocrystalline silicon substrate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; after the cleaning, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and after the chemical vapor depositing, transforming at least a portion of the non-polycrystalline silicon to a polycrystalline silicon mass which is spaced from the substrate surface.
Claim 5
Dependent Claim
22 words
The method of claim 2 wherein the transforming comprises annealing the non-polycrystalline silicon layer at a temperature of at least 550° C.
Claim 6
Dependent Claim
28 words
The method of claim 2 wherein the transforming comprises annealing the non-polycrystalline silicon layer at a temperature of from 550° C. to 750° C. in an inert atmosphere.
Claim 7
Dependent Claim
39 words
The method of claim 2 wherein the cleaning is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing.
Claim 8
Dependent Claim
56 words
The method of claim 2 wherein the transforming comprises annealing the non-polycrystalline silicon layer at a temperature of at least 550° C., wherein the annealing is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the chemical vapor depositing and annealing.
Claim 9
Dependent Claim
90 words
The method of claim 2 wherein, the cleaning is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing; and the transforming comprises annealing the non-polycrystalline silicon layer at a temperature of at least 550° C., wherein the annealing is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the chemical vapor depositing and annealing.
Claim 10
Independent Claim
133 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising: providing outer exposed surfaces of the monocrystalline silicon substrate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; and after the cleaning, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprising varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 11
Independent Claim
133 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising: providing outer exposed surfaces of the monocrystalline silicon substrate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; and after the cleaning, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprising varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 12
Independent Claim
162 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising: providing a transistor gate over the monocrystalline silicon substrate; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; within a rapid thermal chemical vapor deposition reactor and after the cleaning, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and heating the doped non-polycrystalline silicon layer to form a doped monocrystalline silicon region and a doped polycrystalline silicon region, with an interface between said doped monocrystalline region and said doped polysilicon region, said doped monocrystalline region lying between said interface and said monocrystalline substrate.
Claim 13
Independent Claim
162 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising: providing a transistor gate over the monocrystalline silicon substrate; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; within a rapid thermal chemical vapor deposition reactor and after the cleaning, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and heating the doped non-polycrystalline silicon layer to form a doped monocrystalline silicon region and a doped polycrystalline silicon region, with an interface between said doped monocrystalline region and said doped polysilicon region, said doped monocrystalline region lying between said interface and said monocrystalline substrate.
Claim 14
Dependent Claim
39 words
The method of claim 9 wherein the cleaning is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing.
Claim 15
Dependent Claim
56 words
The method of claim 9 wherein the heating comprises heating the non-polycrystalline silicon layer to a temperature of at least 550° C., wherein the heating is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the chemical vapor depositing and heating.
Claim 16
Dependent Claim
90 words
The method of claim 9 wherein, the cleaning is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing; and the heating comprises heating the non-polycrystalline silicon layer to a temperature of at least 550° C., wherein the heating is conducted within a same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing, the substrate not being removed from the reactor between the chemical vapor depositing and heating.
Claim 17
Independent Claim
183 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate; forming an insulating layer outwardly of the gate and the monocrystalline substrate; etching contact openings through the insulating layer to expose monocrystalline silicon substrate surfaces proximate the transistor gate; cleaning the exposed substrate surfaces to remove oxide and impurities therefrom; within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and heating the doped non-polycrystalline silicon layer to form a doped monocrystalline silicon region and a doped polycrystalline silicon region with an interface between said doped monocrystalline region and said doped polysilicon region, said doped monocrystalline region lying between said interface and said monocrystalline substrate.
Claim 18
Independent Claim
183 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate; forming an insulating layer outwardly of the gate and the monocrystalline substrate; etching contact openings through the insulating layer to expose monocrystalline silicon substrate surfaces proximate the transistor gate; cleaning the exposed substrate surfaces to remove oxide and impurities therefrom; within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and heating the doped non-polycrystalline silicon layer to form a doped monocrystalline silicon region and a doped polycrystalline silicon region with an interface between said doped monocrystalline region and said doped polysilicon region, said doped monocrystalline region lying between said interface and said monocrystalline substrate.
Claim 19
Independent Claim
161 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; and within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 20
Independent Claim
161 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; and within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 21
Independent Claim
178 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate; forming an insulating layer outwardly of the gate and the monocrystalline substrate; etching contact openings through the insulating layer to expose monocrystalline silicon substrate surfaces proximate the transistor gate; cleaning the exposed substrate surfaces to remove oxide and impurities therefrom; and within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprising varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 22
Independent Claim
178 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate; forming an insulating layer outwardly of the gate and the monocrystalline substrate; etching contact openings through the insulating layer to expose monocrystalline silicon substrate surfaces proximate the transistor gate; cleaning the exposed substrate surfaces to remove oxide and impurities therefrom; and within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprising varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
References Cited (Backward Citations)
US3681668A
Cited
JPS59189677A
Cited
US5213991A
Cited
US4966861A
Cited
US5079180A
Cited
US5321306A
Cited
US4948745A
Cited
US5057899A
Cited
US5296388A
Cited
US5378651A
Cited
US5250454A
Cited
US5496750A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-05-02 | 2003-11-01 | 2004-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-02 | 2007-11-01 | 2008-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-02 | 2011-11-01 | 2012-05-02 | $7700.00 | Window Closed / Lapsed |