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US6100787A Expired / Lapsed US ⏱️ 0.0 years remaining

Multilayer ceramic package with low-variance embedded resistors

Assignee: NXP USA Inc
•
Filing: 1997-05-28
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Granted: 2000-08-08
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Expires: 2017-05-28
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Abstract

Abstract A multilayer electronic component (200) is provided. The component includes a substrate package assembly (202) with a set of stacked insulated sheets of a dielectric ceramic material (204, 206, 208, 210, 212). Also included are a set of embedded resistors (214), each of the embedded resistors including an electrical input port pad (216) and an electrical output port pad (218) provided in layers between the set of stacked insulated sheets. Each of the insulated sheets has a trough (220) of a predetermined length aligned between and transverse to the electrical input port pad (216) and the electrical output port pad (218). The trough (220) reduces the resistance value variability in the multilayer electronic component (200). The trough (220) is substantially filled with a resistive paste material and an internal circuit (222) connects the embedded resistors inside the substrate package assembly (202). A method of forming the substrate package assembly (202) is also provided.

Inventors

  • 👤 Rong-Fong Huang
  • 👤 Robert A. Burr

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:02
CPC Classifications
H; H01; H01C; H01C13/00; H01C13/02; H05; H05K; H05K1/00; H05K1/16; H05K1/167; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H05K1/02; H05K1/03; H05K1/0306; H05K1/09; H05K1/092; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09654; H05K2201/09672; H05K2201/10; H05K2201/10007; H05K2201/10045; H05K2203/00; H05K2203/14; H05K2203/1453; H05K3/00; H05K3/46; H05K3/4611; H05K3/4626; H05K3/4629

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 114 words
A multilayer electronic component, comprising: a substrate package assembly comprising a plurality of stacked insulated sheets of a dielectric ceramic material; a plurality of horizontally embedded resistors, each of the horizontally embedded resistors defining a resistor formed in only one discrete layer of the substrate package and comprising: an electrical input port pad and an electrical output port pad on a single layer of the plurality of stacked insulated sheets; a trough having a predetermined length and a predetermined width filled with a resistive paste material and providing a uniform resistance across the electrical input port pad and the electrical output port pad; and an internal circuit connecting the plurality of horizontally embedded resistors.
Claim 2
Dependent Claim 114 words
A multilayer electronic component, comprising: a substrate package assembly comprising a plurality of stacked insulated sheets of a dielectric ceramic material; a plurality of horizontally embedded resistors, each of the horizontally embedded resistors defining a resistor formed in only one discrete layer of the substrate package and comprising: an electrical input port pad and an electrical output port pad on a single layer of the plurality of stacked insulated sheets; a trough having a predetermined length and a predetermined width filled with a resistive paste material and providing a uniform resistance across the electrical input port pad and the electrical output port pad; and an internal circuit connecting the plurality of horizontally embedded resistors.
Claim 3
Dependent Claim 21 words
The multilayer electronic component of claim 1, wherein the trough comprises at least two of the plurality of stacked insulated sheets.
Claim 4
Dependent Claim 28 words
The multilayer electronic component of claim 1, wherein the electrical input port pad and the electrical output port pad define an area which is greater than the trough.
Claim 5
Dependent Claim 16 words
The multilayer electronic component of claim 1, wherein the resistive paste material comprises RuO 2 .
Claim 6
Dependent Claim 17 words
The multilayer electronic component of claim 1, wherein the trough has a depth dimension of 7-10 mils.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-08-08 2004-02-07 2004-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-08-08 2008-02-07 2008-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-08-08 2012-02-07 2012-08-08 $7700.00 Window Closed / Lapsed

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