← Back to Patent Explorer
US5371029A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for making a leadless chip resistor capacitor carrier using thick and thin film printing

Assignee: National Semiconductor Corp
•
Filing: 1993-03-24
•
Granted: 1994-12-06
•
Expires: 2013-03-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A process for forming a leadless chip resistor capacitor carrier by forming a first capacitor plate using a first thick film printing sequence and forming the second capacitor plate using a second thin film printing sequence.

Inventors

  • 👤 Azzam A. Abdo
  • 👤 Anwar A. Mohammed

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:24
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/69; H10W70/692; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H10W44/00; H10W44/401; H10W44/601; H10W90/00; H05K1/0213; H05K1/0216; H05K1/023; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/10; H05K2201/10007; H05K2201/10015; H05K2201/10022; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3442; H05K3/36; H05K3/368; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 191 words
A method of manufacturing a carrier for carrying one or more integrated circuits and passive elements, the method comprising the steps of: forming through holes at selected locations of a blank substrate having a top and a bottom surface; forming selectively patterned electrical surface contacts on said bottom surface of said carrier using a printing sequence and metallic paste; applying a vacuum to said top surface to suck metallic paste through said holes; forming a selectively patterned metallization interconnect on said top surface of said carrier using said printing sequence; forming passive elements including a capacitor electrically coupled to said metallization interconnect on said top surface of said carrier; said capacitor being formed by the steps of: forming a first capacitor plate on said substrate during a first thick film printing sequence; depositing a dielectric material on said first plate; forming a second capacitor plate on said dielectric material during a second thin film printing sequence; electrically coupling said metallization interconnect on said top surface to said electrical surface contacts on said bottom surface through said holes of said carrier; and placing a lid on said top surface of said carrier.
Claim 2
Independent Claim 191 words
A method of manufacturing a carrier for carrying one or more integrated circuits and passive elements, the method comprising the steps of: forming through holes at selected locations of a blank substrate having a top and a bottom surface; forming selectively patterned electrical surface contacts on said bottom surface of said carrier using a printing sequence and metallic paste; applying a vacuum to said top surface to suck metallic paste through said holes; forming a selectively patterned metallization interconnect on said top surface of said carrier using said printing sequence; forming passive elements including a capacitor electrically coupled to said metallization interconnect on said top surface of said carrier; said capacitor being formed by the steps of: forming a first capacitor plate on said substrate during a first thick film printing sequence; depositing a dielectric material on said first plate; forming a second capacitor plate on said dielectric material during a second thin film printing sequence; electrically coupling said metallization interconnect on said top surface to said electrical surface contacts on said bottom surface through said holes of said carrier; and placing a lid on said top surface of said carrier.
Claim 3
Dependent Claim 15 words
The method of claim 1, further comprising the step of actively trimming said passive device.
Claim 4
Dependent Claim 21 words
The method of claim 1, wherein said step of forming through holes comprises the step of laser scribing said blank substrate.
Claim 5
Dependent Claim 17 words
The method of claim 1, wherein said step of forming through holes comprises a green punch process.
Claim 6
Dependent Claim 60 words
The method of claim 1, wherein said printing sequence further comprises the steps of: washing the substrate to remove impurities; selectively printing the substrate to form said electrical surface contacts and metallization interconnect; and firing said substrate for a sufficient period of time at a sufficient temperature so that said printed surface contacts and metallization interconnect adheres to said substrate.
Claim 7
Dependent Claim 21 words
The method of claim 5, wherein said substrate is fired at 800 to 1000 degrees C. for 5 to 15 minutes.
Claim 8
Dependent Claim 12 words
The method of claim 1, wherein said passive elements include a resistor.
Claim 9
Dependent Claim 26 words
The method of claim 1, wherein said resistor is formed by the step of selectively depositing a resistive material onto said top surface of said substrate.
Claim 10
Dependent Claim 24 words
The method of claim 1, further comprising the step of attaching a lead to said surface contact on said bottom surface of said carrier.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-12-05 1998-06-06 1998-12-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-12-05 2002-06-06 2002-12-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-12-05 2006-06-06 2006-12-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag