US4372037A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Large area hybrid microcircuit assembly
Assignee: Raytheon Co
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Filing: 1979-12-17
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Granted: 1983-02-08
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Expires: 1999-12-17
Abstract
Abstract A ceramic substrate includes a multiplicity of alternately screened and fired conductor and dielectric levels, with interconnections between levels through small via holes in the dielectric layers or alternately by means of crossovers. Thick film resistors are incorporated throughout the ceramic substrate, wherever needed, and the thick film resistors are printed and trimmed through windows which extend through any upper layers. In addition, resistors may be printed directly on top of the dielectric layers where necessary. Selective area hermetic sealing is utilized only for those chips and wire bonds which require environmental protection by placement of a ring frame seal encircling the selected area and over insulation on substrate conductors which are routed directly beneath the sealing area. A lid is directly soldered to the frame and, before final sealing, a proper environment is created within a sealed area. Where equivalent chip versions of electronic components are not available, discrete components are soldered directly to the ceramic substrate outside of the sealed area. Necessary thermal dissipation can be afforded by direct mounting of the multilevel substrate on a heat sink.
Inventors
- 👤 Robert Y. Scapple
- 👤 Frank Z. Keister
- 👤 Robert G. Grieger
- 👤 Richard P. Himmel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:48
CPC Classifications
H; H05; H05K; H05K5/00; H05K5/0091; H05K5/0095; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K1/00; H05K1/02; H05K1/03; H05K1/0306; H05K1/16; H05K1/167; H05K2201/00; H05K2201/10; H05K2201/10227; H05K2201/10371; H05K2203/00; H05K2203/17; H05K2203/171; H05K2203/30; H05K2203/304; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49087; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49146
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
271 words
A method for fabricating a large area hybrid microcircuit assembly comprising the steps of: placing thick film multilevel conductor, resistor and dielectric patterns on a substrate, including at least one selected area for later placing of electronic components to be hermetically sealed therein; trimming all of the resistors in the patterns; placing at least one closed loop of thick film dielectric material around the selected area, and over all input, output and ground leads extending from the patterns and terminating within the selected area; placing a closed loop of thick film sealing metal over each dielectric material closed loop in which the sealing metal consists of a solderable composition which is compatible with the dielectric material; securing a closed ring frame to each sealing metal closed loop by a first solder consisting of a composition which is sufficiently ductile for militating against fracture and leakage thereof; electrically and mechanically securing any discrete electrical components to the patterns and the substrate outside of the selected area; mounting the electronic components to the substrate within the selected area and the closed ring frame, and electrically coupling the components to the input, output and ground leads therein; sealing a cover to each closed ring by a second solder consisting of a composition which is capable of forming a hermetic seal and withstanding thermal and mechanical shock and repeated temperature cycles such as from -65° to 150° C., and which has a melting point lower than the first solder, and providing a non-reactive environment within the sealed selected area for safeguarding the electronic components from otherwise degrading environment; and electrically and environmentally testing the assembly.
Claim 2
Independent Claim
271 words
A method for fabricating a large area hybrid microcircuit assembly comprising the steps of: placing thick film multilevel conductor, resistor and dielectric patterns on a substrate, including at least one selected area for later placing of electronic components to be hermetically sealed therein; trimming all of the resistors in the patterns; placing at least one closed loop of thick film dielectric material around the selected area, and over all input, output and ground leads extending from the patterns and terminating within the selected area; placing a closed loop of thick film sealing metal over each dielectric material closed loop in which the sealing metal consists of a solderable composition which is compatible with the dielectric material; securing a closed ring frame to each sealing metal closed loop by a first solder consisting of a composition which is sufficiently ductile for militating against fracture and leakage thereof; electrically and mechanically securing any discrete electrical components to the patterns and the substrate outside of the selected area; mounting the electronic components to the substrate within the selected area and the closed ring frame, and electrically coupling the components to the input, output and ground leads therein; sealing a cover to each closed ring by a second solder consisting of a composition which is capable of forming a hermetic seal and withstanding thermal and mechanical shock and repeated temperature cycles such as from -65° to 150° C., and which has a melting point lower than the first solder, and providing a non-reactive environment within the sealed selected area for safeguarding the electronic components from otherwise degrading environment; and electrically and environmentally testing the assembly.
Claim 3
Dependent Claim
36 words
A method as in claim 1 further comprising the steps of removing the cover from the closed ring frame for effecting repairs without thermally damaging the electronic components as a result of the second solder composition.
Claim 4
Dependent Claim
26 words
A method as in claim 1 wherein said multilevel resistor and conductor placing step comprises the steps of screening and firing the patterns on the substrate.
Claim 5
Dependent Claim
89 words
A method as in claim 1 wherein said closed ring frame securing step and said cover sealing step comprises soldering steps in which the sealing metal closed loop comprises one of a thick film platinum-silver alloy paste, or a platinum-gold alloy, and tinned with Sn10 solder alloy, in which the closed ring frame comprises one of metallized alumina ceramic, an iron-nickel-cobalt alloy, or a cold rolled steel alloy, and in which the cover comprises one of an iron-nickel-cobalt alloy electroplated with gold-over-nickel or electroplated with tin-over-nickel and subsequently fused.
Claim 6
Dependent Claim
34 words
A method as in claim 1 wherein said steps of providing a non-reactive environment comprises the step of soldering the cover to the closed ring frame in a dry box in a nitrogen atmosphere.
References Cited (Backward Citations)
FR2118752A5
Cited
GB1369627A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-07 | 1986-08-09 | 1987-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-07 | 1990-08-09 | 1991-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-07 | 1994-08-09 | 1995-02-08 | $7700.00 | Window Closed / Lapsed |