Via connection with thin resistivity layer

Claim 1

A method of forming via connections in an integrated circuit comprising, forming a first level of first electrically conductive lines connected to individual circuit elements on a semiconductor chip, applying a layer of insulative material on said first level, creating a plurality of holes in said layer of insulative material, said holes being formed over and exposing portions of said first electrically conductive lines, depositing a thin layer of electrically conductive material in said holes, said thin layer contacting said first conductive lines, said thin layer characterized by a resistivity in a range from about 10 to about 50 times a resistivity of said first conductive lines and a thinness in a range of between 50 nanometers and 100 nanometers, and forming a second level of second electrically conductive lines, said second lines extending into said holes into contact with said thin layer, said second lines having a resistivity which is approximately equal to said resistivity of said first lines, whereby said thin layer of electrically conductive material in said holes determines local current density of a current conducted through said holes between said first lines to said second lines.

Claim 2

A method of forming via connections in an integrated circuit comprising, forming a first level of first electrically conductive lines connected to individual circuit elements on a semiconductor chip, applying a layer of insulative material on said first level, creating a plurality of holes in said layer of insulative material, said holes being formed over and exposing portions of said first electrically conductive lines, depositing a thin layer of electrically conductive material in said holes, said thin layer contacting said first conductive lines, said thin layer characterized by a resistivity in a range from about 10 to about 50 times a resistivity of said first conductive lines and a thinness in a range of between 50 nanometers and 100 nanometers, and forming a second level of second electrically conductive lines, said second lines extending into said holes into contact with said thin layer, said second lines having a resistivity which is approximately equal to said resistivity of said first lines, whereby said thin layer of electrically conductive material in said holes determines local current density of a current conducted through said holes between said first lines to said second lines.

Claim 10

A method of forming via connections in integrated circuit wafers comprising, forming a first metal layer of first electrically conductive lines connected to individual circuit elements on a patterned semiconductor wafer having a first insulative layer thereover, said first lines characterized by a line resistivity, applying a second layer of insulative material over said first metal layer, patterning a plurality of via holes in said second insulative layer, said via holes being located above and exposing selected portions of said first lines, applying a thin layer of electrically resistive material over said layer of insulative material, said thin layer extending into and lining the bottom of said via holes and contacting said exposed selected portions of said first lines, the thin layer characterized by a resistivity in a range from about 10 to about 50 times said line resistivity and a thinness in a range of between 50 nanometers and 100 nanometers, and forming a second metal layer of second electrically conductive lines, said second lines extending into said holes into contact with said thin layer, said second lines characterized by a resistivity approximately equal to said line resistivity of said first lines, whereby said thin layer acts to control peak current density about said via holes when current is conducted within an integrated circuit wafer.

Claim 11

A method of forming via connections in integrated circuit wafers comprising, forming a first metal layer of first electrically conductive lines connected to individual circuit elements on a patterned semiconductor wafer having a first insulative layer thereover, said first lines characterized by a line resistivity, applying a second layer of insulative material over said first metal layer, patterning a plurality of via holes in said second insulative layer, said via holes being located above and exposing selected portions of said first lines, applying a thin layer of electrically resistive material over said layer of insulative material, said thin layer extending into and lining the bottom of said via holes and contacting said exposed selected portions of said first lines, the thin layer characterized by a resistivity in a range from about 10 to about 50 times said line resistivity and a thinness in a range of between 50 nanometers and 100 nanometers, and forming a second metal layer of second electrically conductive lines, said second lines extending into said holes into contact with said thin layer, said second lines characterized by a resistivity approximately equal to said line resistivity of said first lines, whereby said thin layer acts to control peak current density about said via holes when current is conducted within an integrated circuit wafer.