US4057894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controllably valued resistor
Assignee: RCA Corp
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Filing: 1976-02-09
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Granted: 1977-11-15
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Expires: 1996-02-09
Abstract
Abstract A monolithic semiconductor device including a resistor comprising a first region of one type conductivity, has means for controllably establishing the value of the resistor comprising two additional regions of the opposite type conductivity disposed respectively on opposite sides of the conductive path of the resistor, whereby the width of the resistor is defined by the extent of the additional regions into the first region. Where the monolithic semiconductor device comprises an integrated circuit device including a lateral transistor, the additional regions may be formed simultaneously with the emitter and collector regions of the transistor while utilizing the same doping mask, whereby any variation in the base width of the transistor is made proportional to the variation in the width of the resistor. Such a resistor has a value proportional to the beta of the transistor and may be utilized with circuit means for connecting the resistor with the transistor to compensate for a variation in the base width of the transistor.
Inventors
- 👤 Heshmat Khajezadeh
- 👤 Stephen Carl Ahrens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:53
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/619; H10D1/00; H10D1/40; H10D1/43; H10D84/01; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
188 words
In a method of making a monolithic semiconductor device having a resistor disposed adjacent to a planar surface thereof, which method includes forming a first region of one type conductivity adjacent to said surface and forming two spaced ohmic contacts thereto, the improvement including steps for controllably establishing the value of said resistor comprising: forming said first region in a second region of said one type conductivity disposed adjacent to said surface, said second region having a lower impurity concentration than said first region, whereby the conductive path of said resistor is contained within the more-heavily-doped first region, and forming two additional regions of said opposite type conductivity respectively on opposite sides of said conductive path adjacent to both said surface and the junction between said first and said second regions, said additional regions having a higher impurity concentration and a greater depth than said first region and extending into said first region, whereby the width of said resistor, as measured along the perpendicular to said conductive path at various locations along said conductive path, is established by the extent of said additional regions into said first region.
Claim 2
Dependent Claim
188 words
In a method of making a monolithic semiconductor device having a resistor disposed adjacent to a planar surface thereof, which method includes forming a first region of one type conductivity adjacent to said surface and forming two spaced ohmic contacts thereto, the improvement including steps for controllably establishing the value of said resistor comprising: forming said first region in a second region of said one type conductivity disposed adjacent to said surface, said second region having a lower impurity concentration than said first region, whereby the conductive path of said resistor is contained within the more-heavily-doped first region, and forming two additional regions of said opposite type conductivity respectively on opposite sides of said conductive path adjacent to both said surface and the junction between said first and said second regions, said additional regions having a higher impurity concentration and a greater depth than said first region and extending into said first region, whereby the width of said resistor, as measured along the perpendicular to said conductive path at various locations along said conductive path, is established by the extent of said additional regions into said first region.
Claim 3
Dependent Claim
144 words
A method as recited in claim 1 wherein said device is a monolithic integrated circuit device, wherein said method further includes forming a lateral transistor having spaced emitter and collector regions of said opposite type conductivity adjacent to said planar surface, said device further including circuit means electrically connected to said ohmic contacts and said emitter and said collector regions for connecting said resistor with said transistor to compensate for a variation in the base width of said transistor, and wherein the step of forming said additional regions and a step of forming said emitter and said collector regions of said transistor are performed simultaneously utilizing the same doping mask, whereby any variation in the base width of said transistor, as measured by the distance between said emitter and said collector regions, is made proportional to the variation in said width of said resistor.
Claim 4
Independent Claim
179 words
A method of achieving a plurality of lateral transistors having similar base currents when subjected to identical operating potentials, each of said transistors being disposed adjacent to a planar surface of a separate monolithic integrated circuit device and having spaced emitter and collector regions of one type conductivity adjacent to said surface and a base width as measured by the distance between said emitter and said collector regions, comprising: forming in each of said devices a resistor including a first region of an opposite type conductivity adjacent to said surface and having a first and second ohmic contact thereto, the width of each of said resistors being formed simultaneously with said emitter and said collector regions of the lateral transistor disposed in said device therewith, and electrically connecting said resistor with said transistor in each of said devices by utilizing circuit means connected to said ohmic contacts and said emitter and said collector regions for connecting said resistor with said transistor to compensate for variations in base width in said lateral transistors, whereby similar base currents may be achieved.
Claim 5
Independent Claim
179 words
A method of achieving a plurality of lateral transistors having similar base currents when subjected to identical operating potentials, each of said transistors being disposed adjacent to a planar surface of a separate monolithic integrated circuit device and having spaced emitter and collector regions of one type conductivity adjacent to said surface and a base width as measured by the distance between said emitter and said collector regions, comprising: forming in each of said devices a resistor including a first region of an opposite type conductivity adjacent to said surface and having a first and second ohmic contact thereto, the width of each of said resistors being formed simultaneously with said emitter and said collector regions of the lateral transistor disposed in said device therewith, and electrically connecting said resistor with said transistor in each of said devices by utilizing circuit means connected to said ohmic contacts and said emitter and said collector regions for connecting said resistor with said transistor to compensate for variations in base width in said lateral transistors, whereby similar base currents may be achieved.
Claim 6
Dependent Claim
214 words
A method as recited in claim 3 wherein said step of forming said resistor in each of said devices is performed by: forming said first region in a second region of said opposite type conductivity disposed adjacent to said surface, said second region having a lower impurity concentration than said first region, whereby the conductive path of said resistor is contained within the more-heavily-doped first region, and forming in each of said devices two additional regions of said one type conductivity respectively on opposite sides of said conductive path adjacent to both said surface and the junction between said first and said second regions, said additional regions having a higher impurity concentration and a greater depth than said first region and extending into said first region, whereby the width of each of said resistors, as measured along the perpendicular to said conductive path at various locations along said conductive path, is established by the extent of said additional regions into said first region, said additional regions being formed simultaneously in each of said devices with said emitter and said collector regions while utilizing the same doping mask, whereby the variation in base width of each of said transistors is made proportional to the variation in width of the resistor disposed in said device therewith.
Claim 7
Dependent Claim
43 words
A method as recited in claim 3 wherein said circuit means comprises: a first conductor connecting said first ohmic contact of said resistor to said emitter region, and a second conductor connecting said second ohmic contact of said resistor to said collector region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-14 | 1981-05-16 | 1981-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-14 | 1985-05-16 | 1985-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-14 | 1989-05-16 | 1989-11-15 | $7700.00 | Window Closed / Lapsed |