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US4486738A Expired / Lapsed US ⏱️ 0.0 years remaining

High reliability electrical components

Assignee: Coors Electronic Package Co
•
Filing: 1982-02-16
•
Granted: 1984-12-04
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Expires: 2002-02-16
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Abstract

Abstract An array of electrically interconnected spaced electrical components on an apertured substrate wafer, each component being connected to terminal conductor pads on one surface of the substrate and to terminal conductor pads on the opposite surface of the substrate by thick film conductor strips which extend along the walls of the apertures is disclosed.

Inventors

  • 👤 James L. Sadlo
  • 👤 Gary D. Musil

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 21:14
CPC Classifications
H; H01; H01C; H01C17/00; H01C17/006; H05; H05K; H05K1/00; H05K1/02; H05K1/09; H05K1/092; H05K3/00; H05K3/0097; H05K3/40; H05K3/403; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49099; Y10T29/49789; Y10T29/4979

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 134 words
An array of electrically interconnected spaced electrical circuit components comprising a substrate of electrically insulating material having upper and lower planar surfaces, a plurality of through apertures aligned in at least two parallel rows, both said rows and apertures being spaced apart from each other in said substrate, a continuous conductive ink strip surrounding each aperture and aligned with the aperture row on said upper and lower surfaces of said substrate, a conductive ink strip lining the wall of each aperture and being electrically interconnected to the conductive ink strip surrounding each said aperture and a plurality of electrical circuit components on said upper surface of said substrate aligned in a transverse row each positioned between a pair of apertures and being electrically interconnected to the conductive ink strip surrounding said pair of apertures.
Claim 2
Dependent Claim 134 words
An array of electrically interconnected spaced electrical circuit components comprising a substrate of electrically insulating material having upper and lower planar surfaces, a plurality of through apertures aligned in at least two parallel rows, both said rows and apertures being spaced apart from each other in said substrate, a continuous conductive ink strip surrounding each aperture and aligned with the aperture row on said upper and lower surfaces of said substrate, a conductive ink strip lining the wall of each aperture and being electrically interconnected to the conductive ink strip surrounding each said aperture and a plurality of electrical circuit components on said upper surface of said substrate aligned in a transverse row each positioned between a pair of apertures and being electrically interconnected to the conductive ink strip surrounding said pair of apertures.
Claim 3
Dependent Claim 36 words
An array as claimed in claim 1 wherein said conductive ink strip comprise parallelly extending strips of conductive ink superposed over the parallel rows of apertures, said apertures being centered within said strips of conductive ink.
Claim 4
Dependent Claim 40 words
An array as claimed in claim 1 wherein said conductive ink strip comprise spaced parallel rows of square dots of conductive ink superposed over said spaced parallel rows of apertures, said apertures being centered within said dots of conductive ink.

References Cited (Backward Citations)

US2848359A Cited
GB1087405A Cited
US3775725A Cited
US3659245A Cited
US3964087A Cited
US4199745A Cited
US4278706A Cited
US4294648A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-12-04 1988-06-04 1988-12-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-12-04 1992-06-04 1992-12-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-12-04 1996-06-04 1996-12-04 $7700.00 Window Closed / Lapsed

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