US6033958A
Expired / Lapsed
US
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Method of fabricating dual voltage MOS transistors
Assignee: United Microelectronics Corp
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Filing: 1998-06-30
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Granted: 2000-03-07
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Expires: 2018-06-30
Abstract
Abstract A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.
Inventors
- 👤 Jih-Wen Chou
- 👤 Cheng-Han Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:35
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
181 words
A method of forming dual voltage metal-oxide-semiconductors, comprising the steps of: providing a substrate having a first device region and a second device region defined by an isolation structure; forming a first gate oxide layer having a first thickness, a first polysilicon layer, and a silicon nitride layer sequentially on the substrate; patterning the silicon nitride layer, the first polysilicon layer, and the first gate oxide layer to expose the second device region; thermally oxidizing a surface of the second device region to form a second gate oxide layer with a second thickness different from the first thickness, wherein the second gate oxide layer is not formed over the first device region; removing the silicon nitride layer to expose the first polysilicon layer; forming a second polysilicon layer covering at least the second gate oxide layer; patterning the first and the second polysilicon layer to form a first gate on the first gate oxide layer and a second gate on the second gate oxide layer; and forming a source/drain region in the first device region and the second device region, respectively.
Claim 2
Independent Claim
181 words
A method of forming dual voltage metal-oxide-semiconductors, comprising the steps of: providing a substrate having a first device region and a second device region defined by an isolation structure; forming a first gate oxide layer having a first thickness, a first polysilicon layer, and a silicon nitride layer sequentially on the substrate; patterning the silicon nitride layer, the first polysilicon layer, and the first gate oxide layer to expose the second device region; thermally oxidizing a surface of the second device region to form a second gate oxide layer with a second thickness different from the first thickness, wherein the second gate oxide layer is not formed over the first device region; removing the silicon nitride layer to expose the first polysilicon layer; forming a second polysilicon layer covering at least the second gate oxide layer; patterning the first and the second polysilicon layer to form a first gate on the first gate oxide layer and a second gate on the second gate oxide layer; and forming a source/drain region in the first device region and the second device region, respectively.
Claim 3
Dependent Claim
46 words
A method of claim 1, wherein the first thickness is larger than the second thickness, so that the first device region is suitable for use for forming a high voltage device and the second device region is suitable for use for forming a low voltage device.
Claim 4
Dependent Claim
32 words
A method as claimed in claim 1, wherein the first thickness is smaller than the second thickness, so that the first devic is suitable for use of forming a high voltage device.
Claim 5
Dependent Claim
42 words
A method of claim 1, wherein the second polysilicon layer is formed to further cover the first polysilicon layer, so that the first gate comprises a stack of the patterned first polysilicon layer and a part of the patterned second polysilicon layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |