US5888873A — Method of manufacturing short channel MOS devices

Claim 1

Independent Claim 205 words

A method of manufacturing a semiconductor device having an MOS transistor, which method comprises: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer directly on the second insulating layer; patterning the third insulating layer to expose a gate region; heating to form an oxide region in the exposed gate region on the conductive layer, which oxide region comprises a central portion and a bird's, beak portion at each end of the central portion, each bird's beak portion tapering away from the central portion in a lateral direction; removing the second and third insulating layers; implanting impurity ions, using the oxide region as a mask, into the semiconductor substrate to form lightly and heavily doped source and drain regions with a channel region therebetween, whereby the lightly doped source and drain regions are formed in a self-aligned manner under each bird's beak region and the heavily doped source and drain regions are formed adjacent the lightly doped source and drain regions, respectively; and after implanting the impurity ions, patterning the conductive layer by etching to form a gate electrode over the channel region.

Claim 2

Independent Claim 205 words

A method of manufacturing a semiconductor device having an MOS transistor, which method comprises: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer directly on the second insulating layer; patterning the third insulating layer to expose a gate region; heating to form an oxide region in the exposed gate region on the conductive layer, which oxide region comprises a central portion and a bird's, beak portion at each end of the central portion, each bird's beak portion tapering away from the central portion in a lateral direction; removing the second and third insulating layers; implanting impurity ions, using the oxide region as a mask, into the semiconductor substrate to form lightly and heavily doped source and drain regions with a channel region therebetween, whereby the lightly doped source and drain regions are formed in a self-aligned manner under each bird's beak region and the heavily doped source and drain regions are formed adjacent the lightly doped source and drain regions, respectively; and after implanting the impurity ions, patterning the conductive layer by etching to form a gate electrode over the channel region.

Claim 3

Dependent Claim 109 words

The method according to claim 1, wherein the semiconductor device comprises CMOS transistors, which method further comprises: forming the source and drain regions for an n-channel MOS device by implanting arsenic at an implantation energy of about 500 kev to about 700 kev, wherein the heavily doped regions have a concentration of about 5×10 15 to about 8×10 15 atoms/cm 2 ; and forming the source and drain regions for a p-channel MOS device by implanting boron at an implantation energy of about 150 kev to about 200 kev, wherein the resulting heavily doped region has a concentration of about 5×10 5 to about 8×10 15 atoms/cm 2 .

Claim 4

Dependent Claim 70 words

The method according to claim 1, further comprising, after patterning the third insulating layer and before heating: implanting impurity ions under the gate region in a s channel region to form a first impurity region extending to a first depth into the substrate; and implanting impurity ions under the gate region to form a second impurity region extending to a second depth into the substrate greater than the first depth.

Claim 5

Dependent Claim 37 words

The method according to claim 3, wherein: the first impurity region is a shallow channel region for adjusting the threshold voltage of the transistor; and the second impurity region is a well region for preventing punch through.

Claim 6

Dependent Claim 31 words

The method according to claim 1, wherein: the first insulating layer is a gate oxide layer; the second insulating layer comprises silicon oxide; and the third insulating layer comprises silicon nitride.

Claim 7

Dependent Claim 52 words

The method according to claim 5, wherein: the gate oxide has a thickness of about 50 Å to about 150 Å; the second insulating layer has a thickness of about 100 Å to about 400 Å; and the third insulating layer has a thickness of about 100 Å to about 1500 Å.

Claim 8

Dependent Claim 29 words

The method according to claim 1, comprising patterning by etching to remove a portion of the third insulating layer, leaving the second insulating layer exposed on the conductive layer.

Claim 9

Dependent Claim 29 words

The method according to claim 1, comprising patterning by etching to remove a portion of the second and third insulating layers to expose a portion of the conductive layer.

Claim 10

Dependent Claim 194 words

The method according to claim 3, wherein the semiconductor device comprises CMOS transistors, which method further comprises: implanting boron at an implantation energy of about 100 kev to about 200 kev to form said first impurity region, having a concentration of about 0.5×10 11 to about 2×10 12 atoms/cm 2 , in the channel region of an n-channel MOS transistor; implanting boron at an implantation energy of about 270 kev to about 400 kev to form said second impurity region in the channel region having a concentration of about 1×10 12 to about 5×10 12 atoms/cm 2 , of the n-channel MOS transistor; implanting phosphorous or arsenic at an implantation energy of about 150 kev to about 400 kev to form said first impurity region, having a concentration of about 5×10 11 to about 2×10 12 atoms/cm 2 , in the channel region of a p-channel CMOS transistor; and implanting arsenic or phosphorous at an implantation energy of about 750 kev to about 1000 kev to form said second impurity region having a concentration of about 1×10 12 to about 5×10 12 atoms/cm 2 , in the channel region of the p-channel MOS transistor.

Claim 11

Dependent Claim 48 words

The method according to claim 1, comprising heating at a temperature of about 850° C. to about 900° C., for about 60 to about 90 minutes, to form the oxide region having a central portion with a substantially constant thickness of about 75 nm to about 125 nm.

Claim 12

Dependent Claim 24 words

The method according to claim 1, wherein the lightly and heavily doped source and drain regions are formed during a single ion implantation step.

Claim 13

Dependent Claim 55 words

The method according to claim 1, wherein the semiconductor device comprises CMOS transistors, which method further comprises implanting impurity ions to form lightly and heavily doped n-source and drain regions in a single implantation step; and implanting impurity ions to form lightly and heavily doped p-source and drain regions in a single ion implantation step.

Claim 14

Independent Claim 154 words

A method of manufacturing a semiconductor device having a MOS transistor, which method comprises: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer directly on the second insulating layer; patterning the third insulating layer to expose a gate region; implanting impurity ions under the gate region in a channel region to form a first impurity region extending to a first depth into the substrate; implanting impurity ions under the gate region to form a second impurity region of the same conductivity type as the first impurity region extending to a second depth into the substrate greater than the first depths; implanting impurities of the opposite conductivity type as the first impurity region to form source/drain regions; and etching the conductive layer to form a gate electrode after forming the source/drain regions.

Claim 15

Independent Claim 154 words

A method of manufacturing a semiconductor device having a MOS transistor, which method comprises: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer directly on the second insulating layer; patterning the third insulating layer to expose a gate region; implanting impurity ions under the gate region in a channel region to form a first impurity region extending to a first depth into the substrate; implanting impurity ions under the gate region to form a second impurity region of the same conductivity type as the first impurity region extending to a second depth into the substrate greater than the first depths; implanting impurities of the opposite conductivity type as the first impurity region to form source/drain regions; and etching the conductive layer to form a gate electrode after forming the source/drain regions.

Claim 16

Dependent Claim 37 words

The method according to claim 13, wherein: the first impurity region is a shallow channel region for adjusting the threshold voltage of the transistor; and the second impurity region is a well region for preventing punch through.

Claim 17

Dependent Claim 193 words

The method according to claim 14, wherein the semiconductor device comprises CMOS transistors, which method further comprises: implanting boron at an implantation energy of about 100 kev to about 200 kev to form said first impurity region, having a concentration of about 0.5×10 11 to about 2×10 12 atoms/cm 2 , in the channel region of an n-channel MOS transistor; implanting boron at an implantation energy of about 270 kev to about 400 kev to form said second impurity region in the channel region having a concentration of about 1×10 12 to about 5×10 12 atoms/cm 2 , of the n-channel MOS transistor; implanting phosphorous or arsenic at an implantation energy of about 150 kev to about 400 kev to form said first impurity region, having a concentration of about 5×10 11 to about 2×10 12 atoms/cm 2 , in the channel region of a p-channel CMOS transistor; and implanting arsenic or phosphorous at an implantation energy of about 750 kev to about 1000 kev to form said second impurity region having a concentration of about 1×10 12 to about 5×10 12 atoms/cm 2 in the channel region of the p-channel MOS transistor.

Claim 18

Dependent Claim 22 words

The method according to claim 13, wherein: the second insulating layer comprises silicon oxide; and the third insulating layer comprises silicon nitride.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-03-29	2002-09-28	2003-03-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-03-29	2006-09-28	2007-03-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-03-29	2010-09-28	2011-03-30	$7700.00	Window Closed / Lapsed

Method of manufacturing short channel MOS devices

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